/*
 * blocking.v
 *
 * by Kris Breen
 * EE 552 lab 6
 * February 6, 2003
 *
 */

module blocking(clock, x1, x2, y1, y2);
input clock, x1, x2;
output y1, y2;
reg y1, y2;

always @(posedge clock)
begin
  y1 = x1 & y2;  // & is bitwise and
  y2 = x2 | y1;  // | is bitwise or
end

endmodule