In this lab, design something fun.
You may work alone or in groups of 2.
The FLEX10K contains RAM (random access memory) that can be optionally pre-loaded when you configure your chip. If you only read the memory and omit the logic to write to it, you can consider this memory to be ROM. Each of the following three functions is used for both synchronous and asynchronous implementations of rom and ram. While using rom, the only function "lpm_rom" is used. However for ram, there are two functions. "lpm_ram_io" is used for the case of using a single data I/O port (i.e. the port is used for both input and output), and "lpm_ram_dq" (is used for the case of using separate input and output ports.
In order to better understand the use of the functions "lpm_rom" and "lpm_ram" in this tutorial, it is recommended that you read about "lpm_rom" and "lpm_ram" under the help files in maxplus2, including the explanations of the parameters of the functions.
In order to read a rom, some data must be present in the rom. The data are written in a file called "mif" file because its extension is ".mif". Again it is recommended that you read about "mif" files in the Maxplus2 help files.
To illustrate the use of the functions "lpm_rom" and "lpm_ram", two programs, a "mif" file and this tutorial, including two sets of instructions on how to run the programs, are presented. The programs are called "rom.vhd" and "ram.vhd" which respectively illustrate reading rom and reading ram. The "mif" file is called "primes.mif" and the two sets of instructions are found below.
Again, it is recommended that you read the files mentioned above before
you proceed.
Note: When using version 7.23 of maxplus2 at home, you must place quotes
around the constants for some generics, for example:
lpm_numwords => "10",
1) Open maxplus2.
2) On the menu bar, click on "File" then select "Open"
3) In the "Open" window, change the directory to that where you
store your programs.
4) Lower in the "Open" window, select "Text Editor files". Change the
extension option of "Text Editor files" to ".vhd".
5) Highlight the file "rom.vhd" and click "OK" in the "Open" window
or simply double click on the file "rom.vhd".
6) Make the "rom.vhd" window active by clicking anywhere on the window
7) Select on the menu, "File" -> "Project" -> "Set project to current
file" or use the following combination of keys : "Ctrl" + "Shift" + "j"
- the file name above the menu bar changes
to "rom"
- this enables maxplus2 to compile "rom.vhd".
8) On the menu bar, select "maxplus2" -> "Compiler" or you can use
on of the icons below the menu bar. Notice the explanations at the bottom
of the screen as you move the mouse from one icon to another. A "Compiler"
window pops up.
9) Make the "Compiler" window active by clicking on it. Make sure you
do not click on "Start" yet.
10) Select Interfaces -> "VHDL Netlist Reader Settings". A window pops
up. Select on the top of the window "VHDL 1993" and press "OK"
11) Select on the menu bar "Assign" -> "Device". A "Device" window
pops up.
12) In the "Device" window, Unselect "Show Only Fastest Speed Grades".
Select "Maintain Current Synthesis Regardless of Device or Speed Grade
Changes". In the subwindow "Device Family", select FLEX10K. Then in the
subwindow "Devices", select "EPF10K20RC240-4". This is the Altera board
you are using. Press "OK".
13) Go back to the "Compiler" window and press "Start" for compilation.
14) From the menu bar, select "maxplus2" -> "Waveform Editor". A "Waveform
Editor" window pops up.
15) Make sure the "Waveform Editor" window is active. From the menu
bar, select "Node" -> "Enter Nodes from SNF". A window pops up.
16) On the right of the window, press "List". A list of signals is
listed as indicated in the subwindow "Available Nodes and Groups". (Ignore
signals such as rom_data2.) Go down the list and choose "clock[I]" and
press "=>" in the middle of the window. "clock[I]" appears in the subwindow
"Selected Nodes and Groups". Similarly choose "rom_data[O] and press "=>".
(rom_data[O] is the whole array and rom_data0 is the first element in the
array. So we have chosen the whole array instead of element by element.
Now choose counter[B] and transfer it.
17) Press "OK" and notice that the selected signals appear on the "Waveform
Editor".
18) Set the signal "clock" by first highlighting it with the mouse.
Select from the menu, "Edit" -> "Overwrite" -> "clock". Set the period
to 40ns and press "OK".
19) Save the waveform as "rom.scf".
20) From the menu bar, click "maxplus2" -> "Simulator". A "Simulator"
window pops up.
21) Press "Start" in the "Simulator" window. Check the output values
with "primes.mif". They should be the same.
22) Close all the file windows but keep Maxplus2 when you are ready
for the tutorial on ram.
Note: you can re-order the signals on the "Waveform Editor" by dragging one signal with the left mouse button held down and by putting it where you want it to be.
13) Set the signal "clock" by first highlighting it with the mouse.
Select from the menu, "Edit" -> "Overwrite" -> "clock". Set the period
to 40ns and press "OK".
14) Save the waveform window as "ram.scf".
15) From the menu bar, click "maxplus2" -> "Simulator". A "Simulator"
window pops up.
16) Press "Start" in the "Simulator" window. The results of the output
signals "ram_out" can now be checked with the inputs from "primes.mif".
Note that the outputs correspond to the inputs stored in the address. Remember
that the outputs are synchronized with the signal "clock".
17) Note that at 880ns, "write_enable" is permanently low so that no
writing into the ram is performed. Since the counter is still counting,
we see sequentially what has been stored in the ram.
You may submit something that will be in your project, or an application note.
A demonstration implemented on FPGAs must be made to your TA. Your prof doesn't want to miss out on the fun either, if he's around.
You may make use of VHDL code found in past projects or elsewhere providing that acknowledgment is made and your own contribution contribution is significant.
Hand in the regular requirements plus:
For the curious, in this problem, clock skew refers to the difference in the time that a clock edge arrives at the different clock inputs of the pipeline registers (D-flipflops). You have the tools to figure out the other problems, but they will be covered later in class.