Detailed directions for Mentor Graphics tools are given. You will need to be able to use Mentor Graphics for later labs and the project. Mentor Graphics also has a command line interface, which you are welcome to use.
This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be submitted for marking, in which you will create your own design.
Labs are to be done individually. Please feel free to consult the professor, the T.A. or your fellow students for help with tools and concepts. Please review the lab requirements.
You are permitted to hand in code for this lab that contains
"magic numers" and does not use generics.
-- file: pattern1.vhd
-------------------------------------------------
-- Pattern detector
--
library ieee;
use ieee.std_logic_1164.all;
-- detect a non-overlapping pattern of "1101"
-- and count number of occurrences
entity pattern is
port (
reset, clock, bitstream:
in std_ulogic;
match: buffer std_ulogic;
matches: buffer std_logic_vector(6
downto 0)
);
end pattern;
architecture mixed of pattern is
component count7
port( enable, aclr, clock : in std_logic;
q : buffer
std_logic_vector(6 downto 0));
end component;
-- name states after bit pattern already seen
type state_type is (sawnull, saw1, saw11, saw110);
signal state, next_state :state_type;
begin
combinational_logic :process(state,bitstream)
begin
match <= '0';
case state is
when sawnull =>
if bitstream = '1' then
next_state <= saw1;
else
next_state <= sawnull;
end if;
when saw1 =>
if bitstream = '1' then
next_state <= saw11;
else
next_state <= sawnull;
end if;
when saw11 =>
if bitstream = '0' then
next_state <= saw110;
else
next_state <= saw11;
end if;
when saw110 =>
next_state <= sawnull;
if bitstream = '1' then
match <= '1';
end if;
end case;
end process combinational_logic;
state_register :process(reset, clock )
begin
if reset = '1' then
-- reset state
state <= sawnull;
elsif rising_edge(clock)
then
-- advance to next state
state <= next_state;
end if;
end process state_register;
-- structural VHDL
-- instantiate a counter
matchcounter: count7 port map(
enable => match,
aclr =>reset,
clock=>clock,
q=>matches);
end mixed;
Next, the counter.
-- file: counter1.vhd
-------------------------------------------------
-- 7 bit synchronous counter
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count7 is
port(enable, aclr, clock : in std_logic;
q : buffer std_logic_vector(6
downto 0));
end count7;
architecture behaviour of count7 is
begin
counter :process(aclr, clock)
begin
if aclr = '1' then
q <= "0000000";
elsif rising_edge(clock)
then
if enable = '1' then
q <= q + '1';
end if;
end if;
end process counter;
end behaviour;
If you use MAX+PLUS II, the file name and the entity name should be the same.
Create the other file (again specify the library "work") and compile
each.
Click the run button to advance the simulation time further. Now, get a printout:
Try testing your system with the bit sequence "00010110001110111001101101011001011001100111"
or a sequence of your choosing.
Implement this system with a Moore machine and a synchronous reset.
An example follows:
bitstream1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
bitstream2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
match | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
You may use the following entity, or write your own:
entity pattern is
port (
reset, clock, bitstream1,
bitstream2: in std_ulogic;
match: out std_ulogic
);
end pattern;