EE 552 98w 98-2-22

Lab 5: VHDL Synthesis to FPGA

In this lab you will:

design a chip containing a traffic light controller, using VHDL (submit a state diagram)
perform functional simulation without circuit delays
use "Actel Actmap" software to synthesize a netlist from the VHDL code targeted for an FPGA
use "Actel Designer" software to compile, place, and route the netlist, and to extract timing information
simulate your design using extracted circuit delays

Detailed directions for Mentor Graphics and Actel tools are given. If you which, you can complete this lab using the Altera MAX+PLUS II tools (maxplus2 on CEB531 SUNs or nyquist HPs, or sign out CD-1 for installation on your own PC). MAX+PLUS II does not support testbenches or functional simulation, so you may use the waveform editor and skip to post-layout simulation.

Requirements

Design a finite state machine for a traffic light controller for a 4-way intersection with push-to-walk buttons.

The lights normally cycle through: north-south green (5 clock ticks), amber (2), red all directions (1), east-west green (4), amber (2), red all directions (1).
When a push-to-walk button is pressed, even momentarily, and the "other" direction has a green light, then that green light will last one full clock tick after the next active clock edge (unless the light was due to turn before this) before it turns amber.
The 6 outputs are signals controlling the red, amber and green lights in each of the North-South and East-West directions.
The 3 inputs are the clock and the North-South and East-West buttons plus any other signals you feel are required.

Part 1: Design Entry

"%" refers to the C-shell command prompt.
Create the directory ~/ee552/lab5 and set the MGC_WD environment variable:

% mkdir ~/ee552/lab5

% cd ~/ee552/lab5

% setenv MGC_WD `pwd`

NOTE ` is a back quote, usually above the TAB key

Start design architect and enter a VHDL description for the traffic light controller. Examples in the text below assume that the top level design file is called "chip.vhd" and the test bench is called "tester.vhd".

Note that the inbuf, outbuf, and clkbuf will be inserted automatically when "actmap" is used in chip mode on the top level of the hierarchy.

Part 2: Functional Simulation

Simulate your VHDL code using a testbench, also written in VHDL. Use signals of type "std_logic" for the pins of the chip, so as to be compatible with the automatically generated structural VHDL code (including extracted timings) which will represent your design "post-layout". Remember to select (toolbar) Compile => set options and specify the library “work”.

Mentor Graphics will by default use an architecture of an entity if it is the only one found in the library "work". The "actmap" synthesis tool requires that any architectures found in other files be explicitly requested in the architecture which instantiates it. For example, to use architecture "behavioural" of entity "walk_button", use this line of VHDL:

for all: walk_button use entity work.walk_button(behavioural);

Submit the timing wave forms that verify the operation of your circuit.

Part 3: Synthesis and Logic Optimization

With a text editor, create a "project" file starting with the same name as the top level of your VHDL hierarchy (e.g. "chip.prj"). As an example, the file could contain:

chip.vhd

walkbutton.vhd

This file allows one-step synthesis of multiple file projects in "actmap".

The Actel tool "actmap" synthesizes VHDL code into netlists. As you already know, actmap can also optimize netlists.

% actmapw &

(Menu) -> File -> New Design ...

Source Design: (Browse - select chip.prj)
Source Format: VHDL
Family: ACT1
Mode: chip
Minimize: area
flatten

Use this option to instruct Actmap to produce intelligible net names (you may have to turn this option off, though, to track down occasional errors later in qhsim):

menu -> options -> port-option name -> match

The synthesis tool allows some tuning for speed vs. area. The netlist optimizer can do more. Choose the options which favour reduced size and select RUN.

How many logic modules did you start out with and end up with?

Now start over but minimize delay (maximize speed). How have the maximum delays and number of logic modules changed?

Exit actmap and free up the software licence for someone else.

Part 4: Layout and Extracted Timings

You will be using two different VHDL descriptions of your design, the (behavioural) one you entered and the purely structural one as a result of actmap. Use the "_str" suffix to indicate the structural view of the design. Create a symbolic link. Then convert the EDIF netlist into VHDL (without the name change, you would overwrite your original design).

% rm chip_str.edn

{ ignore any file not found message }

% ln -s chip.edo chip_str.edn

% edn2vhdl fam:act1 busdir:down chip_str

Use "Actel Designer" to map the "chip_str.edo" optimized EDIF netlist into an ACT1 FPGA

% designer &

As in the previous lab, compile and layout your design. When you extract the design, specify "Standard Delay Format":

CAE: SDF

Exit designer.

Summarizing, "chip_str.vhd" contains the structural design created by actmap and "chip_str.sdf" contains the delay information for every signal in "chip_str.vhd".

Part 5: Simulating with Extracted Layout Timings

For more information, you may wish to refer to Actel's "VHDL VITAL Simulation Guide", pg 26.

Use the Actel library for simulation

% setenv QUICKHDL /opt1/actel/lib/vtl/95/qhdl/quickhdl.ini

% rm quickhdl.ini

{ ignore any file not found message }

% ln -s $QUICKHDL .

Compile "chip_str.vhd" in design architect

% da &

or use qvhcom and, if you wish, simulate the structural VHDL generated by actmap which contains generic timings not specific to your layout.

Finally, simulate your design with extracted delays for maximum delay process parameters:

% qhsim -sdfmax top_str.sdf &

Using simulation, measure the worst cases for: setup time from data input to clock, maximum clock frequency, and propagation delay from clock to output.