EE 552 98w 98-1-30

Lab 4: Device Mapping and Back-Annotated Simulation

In this lab you will: Use "two's complement" number representation (i.e. "10"=-2, "11"=-1, "00"=0, "01"=1).  You may create a multiplier which takes larger operands if you feel inspired.

Part 1: Design Entry

Create the directory ~/ee552/lab4 and set the MGC_WD environment variable: and start a new sheet called mult2 in design architect.

Using the Actel Libraries

design a 2-bit by 2-bit signed multiplier using schematic capture.  You will still need to use the portin, portout, Vcc, and Gnd symbols from the generic library.

Your circuit should have the input ports: clock, clear, A0, A1, B0, B1 and the output ports: product0 .. product3.  Since you are designing a circuit for implementation on a chip, all inputs and outputs need to be buffered (at the chip pins).  Use D-flipflops to latch all data inputs and outputs. Figure 1 gives an example of the signals flow (but with fewer inputs and outputs, and the combinational logic consists of a single inverter). The data signals should flow from input port through input buffers "inbuf" to D-flipflops, through all combinational logic for the multiplier, to the output D-flipflops, through the output buffers "outbuf" to the output ports. The clock is fed to a special input buffer "clkbuf" which drives the Actel ACT1's low-skew internal clock distribution network. Note: input, output and clock buffers are only used when connecting signals to the chip pins.


figure 1: example chip design

Check and save your design.  Expect some warnings in the "check instance" category, when checking. Fix any other warnings.

Save a back-up copy of your schematic in case you need to return to it later.

 

 Part 2: Functional Simulation

At this time, you will simulate your circuit without timing information to verify only that it is logically correct.

You must now create a viewpoint that can be used to run the simulator. At the command line type:

Once this program has run you can now run quicksim.

To run quicksim from the command line in the directory  ~/ee552/lab4   type;

Select suitable inputs to verify the operation of your multiplier. (Use the "unit delay" simulation kernel.)
Hint: save you simulation stimuli (inputs) for the back-annotated simulation later in this lab.

Submit the timing wave forms that verify the operation of your circuit.
 

Part 3: Device Mapping

In this part, you will compile or device-map your design to the target Actel ACT1 FPGA.

First convert the Mentor schematic to an EDIF netlist, which the Actel tools can process, using the mgc2edn command:

This will create the file mult2.edn which is required in downstream operations.

In order to use the Actel Designer Software at the command line type:

After verifying that a licence is available the Designer Main Screen window called Designer should open after a few moments (Ignore all the warning messages that appear on the screen).

From the menu bar select
 

The  Setup Design dialog box appears:

Make the following selections:

Select the OK button.

The Device Selection dialog box  should then appear:

Make the following selections:

Note: for your project, you have the option to use:
the larger 547 module A1020B (the A1010B contains 295 logic modules),
the larger IC package 68PLCC or
to use the two Probe Pins instead as signal pins by setting “Restrict Probe Pins”=off

The Operating Conditions dialog box will then appear:

Make the following selections:

Select the OK button
 

You are now ready to import your design. Using the menu bar select
 

 
The Import dialog box will then appear:

Select the directory:

Select the input file type:   EDIF (*.edn)
Select the Options... button

 In the Import Netlist Options dialog box that appears,
 
Make the following selections:

 Select the OK button
 Returning to the Import dialog box select the Filter Button at the bottom of the dialog box to complete the File Name as:  Select the OK button

Once the file has been imported you are now ready to run Designer
 

From the Designer Main Screen click on  the Compile Button. This will compile the design, listing how  many modules are required, how many I/O pins, and if there are fan out problems.  You may receive a warning if one output drives more than 10 inputs (fanout of > 10). This may cause the signal to have a larger than average delay.  A fanout of > 24 causes an error and the design will not compile.  How many "input loads" does the clear on a master-slave flipflop contribute to a net?

Selecting the Pin Edit button will bring up a dialog box which can be used to fix I/O pins. Normally we let the software select the optimum placement. (Pins can be fixed by 'dragging'  the pin name to the desired pin location). Once you have viewed the Pin Edit screen  you can close it by

Select the Layout button.

In the Layout dialog box that appears make the following selections:
 

 Then Select the OK button
 

Select the Fuse button.
 
A Fuse dialog box appears.
You may input a five hexadecimal character signature. This is useful for identifying the chip later on. (It is only useful if the probe pins have not been used as I/O pins).
Select

Select the OK button

This will create a mult2.afm file
 

To create a file that can be used for back-annotated timing simulations select the extract button. In the Extract dialog box that appears select:

In the Status box show the following entries Select the OK button
This will create a mult2.stf file.
 

To generate a list of pin assignments select :

Use "sort by pin" then complete the file entry as: Select the OK button.
 
Save the design database: Finally, exit Designer.
Use the menu bar to select;  
 

Part 4: Back-annotated Simulation

In this part, you will merge the timing information from the extracted FPGA design in part 3 with the schematic and resimulate the design.
 

Creating Back Annotated Simulation file
In the directory ~/ee552/lab4, type the command:

Now start design architect and look at the back-anotated delays. You can directly measure combinational delays and flipflop propagation delays using the simulator.  Measuring setup time using the simulator, however, would take trial and error.  Instead, the setup time can be viewed by looking at the properties of each instance of a flipflop.  To view the properties of a circuit element select only the component you are interested.  Then use A list of properties should appear in a window.  You can view them and change them (if required).  If you want, you can select many instances of components and try to view the properties.  A list of common properties should appear.
 

Next open quicksim (with "typical" timing parameters) by typing the command

Use the palette window to open the schematic sheet, select the appropriate input and output portin and portout nets, then open the trace window. Select the simulation kernel "Delay". Run suitable timing wave forms to verify the operation of the circuit.
 

Hint: When simulating it is important to get the right signal.  If you want to look into an instance in quicksim: select the component instance and use 

select "schematic" and press OK.  You can now grab signals from within the
instance and add them to your trace.

Determine the worst case delay from:
1. an input port to the D input of a D-flipflop
2. signal path from D-flipflop through the combinational logic to D-flipflop.  (Measure from the clock edge to the input of the next D-flipflop.) Explain how you found the case (transition from previous data to current data) which produced the worst case delay.
3. signal path from D-flipflop (from the clock edge) to output port.
4. What is the maximum clock frequency (you must include setup time)?  Simulate it.
5. Show the results of all 16 inputs.

Hand in simulations showing all of these measured values. Use the trace window cursors (Function key F5) to measure the delay times.  Write on the timing diagram what you are measuring and the value. Rise times and fall time may not always be equal. Equivalent paths in the circuit will almost always have different delays due to different routing. Be careful when looking for the worst case.
 

Part 5: Logic Optimization

The Actel tool "actmap" can optimize an EDIF netlist (*.edn) for size or speed and generate an optimized EDIF (*.edo) netlist as output.  Try using the optimizer to reduce the number of logic modules used by your multiplier: Choose the options which favour reduced size and select RUN.

How many logic modules did you start out with and end up with?