EE 552 98w 98-1-23

Lab 3: VHDL for Synthesis

In this lab, you will write a behavioural description of a design in VHDL, suitable for synthesis.

Detailed directions for Mentor Graphics tools are given. If you which, you can complete this lab using the Altera MAX+PLUS II tools (maxplus2 on nyquist HPs or sign out CD-1 for installation on your own PC).

Part 1: Finite State Machine Design

Design a system that counts the number of times one pattern of bits has been observed ("1101"), less the number of times another pattern ("11001") has been observed.

The patterns themselves will be detected by a Moore synchronous finite state machine (FSM) as the bits arrive serially through a single bit input. When a match is detected, the "match1101" or "match11001" output should go high for an entire clock cycle following the active clock edge at which the last bit of the pattern was received. Your FSM should detect overlapping instances of these patterns.

Submit a drawing of your FSM.

You may use std_logic, std_ulogic or a mixture. The system will have 4 parts (4 files: tester.vhd, chip.vhd, pattern.vhd, counter.vhd) containing these entities:

-- tester.vhd     The testbench for your entire system below
entity tester is
end tester;

-- chip.vhd    The top-level design file for you system which
--             instantiates the next two files
entity chip is
    generic ( counter_width : positive := 8 );
    port (
        reset, clock, bitstream : in std_logic;
        Q : out std_logic_vector(counter_width-1 downto 0)
    );
end chip;

-- pattern.vhd    The pattern detector
entity pattern is
    port (
        reset, clock, bitstream : in std_logic;
        match1101, match11001 : out std_logic
    );
end pattern;

-- counter.vhd  Synchronous up-down counter with asynchronous reset
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity up_down_counter is 
    generic ( counter_width : positive := 8 );
    port (
        Enable, count_up, reset, Clock : in std_logic;
        Q : buffer std_logic_vector(counter_width-1 downto 0)
    ) ;
end up_down_counter;

Part 2: Design Entry

Login and create a directory “~/ee552/lab3”.
"cd" to this directory.
Set these environment variables from the csh (note the single back-quotes, usually above the tab key on the keyboard).

% setenv MGC_WD `pwd`

% setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini

Invoke Design Architect and select the

(session pallet) “open VHDL” icon Provide the file name “pattern.vhd” in the current directory. Specify the library which your design will be compiled into:

(toolbar) Compile => set options Specify the library “work” in the current directory and select “constraint checking” and “explicit scoping”.
Enter VHDL code for your FSM in the VHDL Editor window.
When finished, try to compile your code. Select:

(VHDL pallet) Compile If you have errors, select the error message and click on “Highlight” to show where the statement appears in your source code. The warning message “Compilation canceled” can actually mean the compile succeeded without errors.

Create the other 3 files (again specify the library “work”) and compile each.
“tester.vhd”, should contain stimuli which illustrate your FSM responding to overlapping patterns, non-overlapping patterns and other data.

Part 3: Simulation

Click on the Design Architect background to deselect all windows. Invoke the VHDL simulator:

(toolbar) QuickHDL => Simulate... Specify your library “work” and the name of the entity of your testbench. From the QuickHDL toolbar, bring up a list of signals

(QuickVHDL toolbar) View => Signals... Now bring up the waveform display with all signals:

(Signals toolbar) Wave => signals in design Click the run button to advance the simulation time and simulate your circuit. Submit a waveform plot showing the correct operation of your FSM:

(Wave toolbar) File => write postscript... You can also manually add stimuli to the simulation. This is useful for debugging individual architectures.

Test your system with the bit sequence "00010110001110111001101101011001011001100111" as well as sequences of your choosing.

Hand in a FSM diagram, VHDL code and simulation output which shows your system working. Write in annotation on the simulation output to show the significance of the tests. Describe the time your design takes from the application of the last bit of the pattern to the raising of the alarm signal.