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Lab 5: Have Fun

 
Requirements for lab assignments

In this lab, design something fun.

 

Exercise

Experiment with memory (lpm_ram_dq).

Lab

Design a digital system that is entertaining to use, or at least entertaining to design.  Don't put more time into this than a regular lab would take.

You may make use of VHDL code found in past projects or elsewhere providing that acknowledgment is made and your own contribution contribution is significant.

Hand in the regular requirements plus:

  1. An explanation of what your design does.
  2. Simulation
  3. Find the maximum speed.  Describe the critical path.  What would you do differently if your design had to be clocked faster?
Here are some random suggestions: