EE 552 98f 98-10-5 press reload

Lab 4: Handshaking Controlling Pipelined Datapaths

In this lab, you will design more elaborate data paths and the handshaking to control them.

Lab

Part A: Tuning Pipelines

Design an unsigned multiplier (8-bit multiplicands, 16-bit product) so as to minimize the following cost function:

cost(#logicCells, latency, throughput) = #logicCells * 10/cell + latency * 1/ns + 100MHz / throughput Design your multiplier without the aid of LPM or any other library of components. You must provide handshaking signals, so it is permissible to have a throughput of less than one result per cycle. You may, for instance, chose a multiplier architecture that re-uses some circuits for multiple cycles, thereby using fewer logic cells but having a lower throughput. The data input and output of your multiplier must be registers in order for registered-performance timing analysis to provide a report for your entire circuit.

Measure the total number of logic cells in the design. Throughput is the maximum clock frequency (MHz). We will define latency as the number of pipeline register stages, not counting the first one, (alternatively, the number of pipeline stages in lpm_mult plus one) times the minimum clock period.

Place the component definition for your multiplier in a package. An example is provided.
Use the following component definition for your multiplier and place it in a package as shown below:

package multiply_pkg is
-- your constant definitions go here
component multiply
    generic(multiplier_width : positive := 8);
    port(a, b : in std_logic_vector(multiplier_width-1 downto 0);
        clock, reset, datain_valid, dataout_request : in std_logic;
        dataout_valid, datain_request : out std_logic;
        product : out std_logic_vector(2*multiplier_width-1 downto 0));
end component multiply;
end package multiply_pkg;

Hints:

The version of maxplus2 on the workstations produces faster smaller designs than the student version
The EE480 course notes contain some suggestions for implementing multipliers (ask your professor)

This is a class competition. Supply the following:

Appropriate text from the fitting report.
Timing analyzer results and simulator output from maxplus2
Note which version of maxplus2 you are using
Cost calculation (put a box around the answer and place it on your title page as well)

Part B: Pipeline Control

Using your multiplier and a counter, create a system which produces the squares of odd numbers from 1 through 31 and then stops producing valid results. Your multiplier should indicate valid output when producing one of the results in the sequence. The counter should count by one when requested to do so (dataout_request) and indicate that its output is valid (dataout_valid) when it produces an odd count less than or equal to 31.

Use the following handshaking scheme:

+----------------------+      +----------------------------------------+
|       dataout_request|<-----|datain_request           dataout_request|<-----
|Counter        dataout|--/-->|datain        Multiplier         dataout|--/-->
|         dataout_valid|----->|datain_valid               dataout_valid|----->
+----------------------+      +----------------------------------------+

The top-level VHDL code is provided. Packages must be supplied for the counter and multiplier.