EE 552 98f 98-9-21 - press reload

Lab 2: VHDL Synthesis and Extracted-Timing Simulation

In this lab, you will design systems in VHDL, synthesize them, extract timing information and simulate using the extracted timing information.

You will be using the Altera MAX+PLUS II tools (maxplus2 is available on the CAD suns, nyquist HPs or sign out CD-1 for installation on your own PC).

This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be
submitted for marking, in which you will create your own design.

Labs are to be done individually. Please feel free to consult the professor, the T.A. or your fellow students for help with tools
and concepts.

Hints

Maxplus2 may start new projects in VHDL-1987 mode. To switch the maxplus2 compiler to VHDL-1993 mode, open/select the compiler window and select:

Interfaces -> VHDL netlist reader settings...

VHDL-1993

In order to set the clock period to any desired value, and not just a multiple of the simulation grid size, open/select the waveform editor window and deselect:

Options -> Snap to Grid

To select the device FLEX EPF10K20RC240-4, used in this lab, select:

Assign -> Device ...

device family: FLEX10K

show only fastest speed grades

EPF10K20RC240-4

Exercise (do not hand in)

Part 1: Become Familiar with MAX+PLUS II

Create a directory for the lab and start maxplus2.

% mkdir ~/ee552/lab2

% cd ~/ee552/lab2

% maxplus2 &

or possibly

% /opt1/maxplus2/bin/maxplus2 &

Work through the student application notes on the maxplus2 editor, device selector, compiler, and simulator.

Part 2: Simulate a Simple Combinational Circuit

Simulate a 4-bit adder compiled for a FLEX EPF10K20RC240-4. Try to determine the inputs (previous values and new values) that produce the maximum delay. What is the maximum delay? What is the maximum number of times the output changes for one change to the input (zoom in on the simulated waveform)?

--------------------
-- Adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
        generic(adder_width :positive := 4);
        port(a,b: in std_logic_vector(adder_width-1 downto 0);
                sum: out std_logic_vector(adder_width downto 0)
        );
end adder;

architecture behavioural of adder is
begin

sum <= a + b;

end behavioural;

Lab

Run all requested simulations with extracted timing for a FLEX EPF10K20RC240-4.

Part 1: Thoughts on Simulation

Exactly how many pairs of previous inputs and new inputs would you have to test to exhaustively determine the maximum delay?
Making reasonable assumptions about the implementation of the adder, what sets of inputs might produce the maximum delay?

Part 2: Simulating Synchronous Circuits

Design a 4-bit counter with clock and asynchronous reset, and a BCD to 7-segment display decoder. The decoder should correctly display 0 through 9. The outputs should be active low.

What is the minimum clock period for which the circuit still perform correctly through all states (values of counter)?
What is the worst-case delay from clock to output?
What is the worst-case delay from reset to output?

Part 3:

Design a circuit, which after n+k clock cycles, produces the output n squared. It should produce the squares of 0 through 15 without overflow. The constant k will depend on your design. Don't use a multiplier. You may use the following C code for inspiration.

/* create a table of squares without using multiplication */

#include <stdio.h>

#define UPPER_LIMIT 15

main(){
int n, nsquared, sum, oldsum;

sum = 0;
oldsum = 0;
for( n=0; n<=UPPER_LIMIT; n++) {
    oldsum = sum;
    sum += n;
    nsquared = sum + oldsum;
    printf("%d squared is %d\n", n, nsquared);
}
exit(0);
}

Incidentally, this is a computing trick from the 1930's used in differential analyzers.

What is the minimum clock period for correct operation?
Why would you want to think of clever ways to avoid performing multiplication in hardware?