EE 552 98f 98-9-14

Lab 1: VHDL for Synthesis

In this lab, you will write a behavioural description of a design in VHDL, suitable for synthesis.

Detailed directions for Mentor Graphics tools are given.  If you wish, you can complete this lab using the Altera MAX+PLUS II tools (maxplus2 on nyquist HPs or sign out  CD-1 for installation on your own PC, see these Student Application Notes).  You can also use the Mentor Graphics tools with the command line interface as you did in EE 480.

This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be submitted for marking, in which you will create your own design.

Labs are to be done individually.  Please feel free to consult the professor, the T.A. or your fellow students for help with tools and concepts.
 

Exercise (do not hand in)

Part 1: Finite State Machine Description

In this exercise, you will simulate behavioural VHDL code for a Mealy machine that detects non-overlapping occurrences of the pattern "1101" and counts up to at least 100 occurrences.  You will copy and paste the following two files into the VHDL editor as described later.

-- file: pattern1.vhd
-------------------------------------------------
-- Pattern detector
--
library ieee;
use ieee.std_logic_1164.all;
 

-- detect a non-overlapping pattern of "1101"
-- and count number of occurrences
entity pattern is
    port (
        reset, clock, bitstream: in std_ulogic;
        match: buffer std_ulogic;
        matches: buffer std_logic_vector(6 downto 0)
    );
end pattern;

architecture mixed of pattern is
 

component count7
    port( enable, aclr, clock : in std_logic;
          q : buffer std_logic_vector(6 downto 0));
end component;

-- name states after bit pattern already seen
type state_type is (sawnull, saw1, saw11, saw110);
signal state, next_state :state_type;
 
 

begin

combinational_logic :process(state,bitstream)
begin

match <= '0';
case state is
        when sawnull =>
                if bitstream = '1' then
                        next_state <= saw1;
                else
                        next_state <= sawnull;
                end if;
        when saw1 =>
                if bitstream = '1' then
                        next_state <= saw11;
                else
                        next_state <= sawnull;
                end if;
        when saw11 =>
                if bitstream = '0' then
                        next_state <= saw110;
                else
                        next_state <= saw11;
                end if;
        when saw110 =>
                next_state <= sawnull;
                if bitstream = '1' then
                        match <= '1';
                end if;
end case;

end process combinational_logic;
 

state_register :process(reset, clock )
begin
        if reset = '1' then
                -- reset state
                state <= sawnull;
        elsif rising_edge(clock) then
                -- advance to next state
                state <= next_state;
        end if;
end process state_register;

-- structural VHDL
-- instantiate a counter

matchcounter: count7 port map(
        enable => match,
        aclr =>reset,
        clock=>clock,
        q=>matches);
 

end mixed;

 

Next, the counter.
 

-- file: counter1.vhd
-------------------------------------------------
-- 7 bit synchronous counter
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 

entity count7 is
    port(enable, aclr, clock : in std_logic;
        q : buffer std_logic_vector(6 downto 0));
end count7;

architecture behaviour of count7 is

begin

    counter :process(aclr, clock)

    begin
        if aclr = '1' then
            q <= "0000000";
        elsif rising_edge(clock) then
            if enable = '1' then
      q <= q + '1'; 
            end if;
        end if;
    end process counter;

end behaviour;
 

If you use MAX+PLUS II, the file name and the entity name should be the same.

Part 2: Design Entry

Login and create a directory "~/ee552/lab3".
"cd" to this directory.
Set these environment variables from the csh (note the  single back-quotes, usually above the tab key on the keyboard). Invoke Design Architect and select the Provide the file name "pattern.vhd" in the current directory. Specify the library which your design will be compiled into: Specify the library "work" in the current directory and select VHDL 93, constraint checking and explicit scoping.
Enter VHDL code for your FSM in the VHDL Editor window.
When finished, try to compile your code. Select: If you have errors, select the error message and click on Highlight to show where the statement appears in your source code. The warning message "Compilation canceled" can actually mean the compile succeeded without errors.

Create the other file (again specify the library "work") and compile each.
 

Part 3: Simulation

Click on the Design Architect background to deselect all windows. Invoke the VHDL simulator: Specify your library "work",  units ns and click OK. In the next dialog box, select the entity "pattern".
From the QuickHDL toolbar, bring up a list of signals Now bring up the waveform display with all signals: Create some simulation stimuli.  In the qsim.mod window, type: The first number in each pair is the signal level and the second is the delay in ns after which the signal is applied.

Click the run button to advance the simulation time further. Now, get a printout:

You can also add stimuli to the simulation from the signals window.  This is useful for debugging individual architectures.

Try testing your system with the bit sequence "00010110001110111001101101011001011001100111" or a sequence of your choosing.
 
 

Lab

Design a system that decrements a count (initially reset to 10) each time the pattern (sequence of all three in order) "3,1,2" is observed at the 2-bit input.

The patterns themselves will be detected by a Moore synchronous finite state machine (FSM). When a match is detected, the "match" output should go high for an entire clock cycle following the active clock edge at which the last portion of the pattern was received.
 
You may use std_logic, std_ulogic or a mixture.  The system will have 3 parts (3 files: chip.vhd, pattern.vhd, counter.vhd)  containing these entities:
-- chip.vhd    The top-level design file for your system which
--             instantiates the next two files
entity chip is
    port (
        reset, clock : in std_logic;
        instream : in std_logic_vector(1 downto 0);
        Q : buffer std_logic_vector(3 downto 0);
    );
end chip;

-- pattern.vhd    The pattern detector
entity pattern is
    port (
        reset, clock : in std_logic;
        instream : in std_logic_vector(1 downto 0);
        match : out std_logic
    );
end pattern;

-- counter.vhd  Synchronous down counter with asynchronous reset
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity down_counter is
    port (
        Enable, reset, Clock : in std_logic;
        Q : buffer std_logic_vector(3 downto 0)
    ) ;
end down_counter;
 

Create an input test pattern that exercises all transitions in your FSM (indicate them).  Write in annotations on the simulation output to show the significance of the tests.  Describe the time your design takes from the application of the changing of the count.

Hand in:

  1. title page
  2. FSM diagram and design assumptions
  3. VHDL code
  4. description of testing technique
  5. simulation output which shows your system working
  6. any feedback on how the lab went