Book: Introduction to VLSI Circuits and Systems, John P. Uyemura
page: 54

- Han-Jen Yang

Error: figure 2.57(b) Besides the pin errors on the XOR gate (fig. 2.57(a)), the pin arrangement on the XNOR gate is also
       incorrect. The arrangement should go like:

       on the PMOS network:

              Vdd

       a(bar)        b
       b(bar)        a

             output

       *p.s. in case, this is still cryptic to you, the correct arrangement is to switch input pin a & b on PMOS network