ECE 553 Digital Integrated Circuit
Design
Winter Term (2012w)
last updated 2012-4-26
Course web page:
http://www.ece.ualberta.ca/~elliott/ece553/
For questions concerning labs 0-3, use the Moodle discussion forum.
Lab announcements
can be found here (and optionally delivered to your email).
Lab
questions can be posted here. If you know the answer to
a question (a difficulty, not a marked course component), by all
means post it. Please read prior postings to see if your
question has been asked and answered. Create a new topic for
most questions (unless it's a request for elaboration).
For questions concerning the lectures or project, see me in class,
during office hours or send email.
Use email for questions of a confidential nature.
General Course Info
Lectures Tues., Thurs. 11:00-12:20 in ECERF w6-087.
Some lectures may be held at different times.
If you prefer, you may work on the labs on your own time, so don't
worry about schedule conflicts (attendance isn't taken).
Lab TA support should be available specified Tuesdays 14:00-16:50.
CAD lab ETLC e5-013 is open
extended hours, use your AICT (campus computer) userid
Office hours
Outline
- Review of Static CMOS Circuits and Simulation
- Review MOS transistor theory
- IC Process Technology
- Parameter extraction and performance estimation
- IC Layout, including transistor sizing and Logical Effort
- Review Logic Circuit Families, Memories
- Synchronous Systems, Clocking and Clock Distribution
- Extreme circuits (pushing the power and speed envelope)
(ask more questions and we'll cover less material but in greater
depth)
Marking
Tentative Marking scheme for ECE 553.
Items [that were] indicated with ?? are tentative and are to be
decided by majority vote in class by deadlines set by instructor.
Bonuses may be available on some marked materials.
| Term work |
35% |
Labs,
Problem Sets due ??Thursdays,
Application Notes
|
| Project |
45% |
Group design of an at least partially digital IC including
a custom design component
Topics offered by instructor, or see me
Mark based on reports and public presentation
Presentation Apr 12
Reports due April 13
|
| Final Exam |
20% |
4 aid sheets 8.5x11 inch, hand written, any information
date determined by class
|
Problem sets are due at
the beginning of lectures. Mutually beneficial
collaboration is encouraged, provided that the names of all
collaborators are cited on the problem set, immediately below the
student's name. Marking may either be based on content or
effort at the instructor's discretion. Please do not put
student id numbers on problem sets or any other materials to be
handed out in class.
Labs must be
completed in groups of one or two (as specified in lab) without
outside assistance beyond general advice on tools (certainly no
sharing of files or printouts). Submissions are due by
3:40 pm in the ECE 553 assignment box in the ECERF-ETLC
atrium. Late submissions will be penalized 20% of the
assigned mark per school day. Labs and problem
sets should be brief but sufficiently clear and readable that you
would be happy to submit them to a busy engineering
manager. If it only takes a sentence to describe something,
then it should be described in a sentence. Assignments
should include:
- Title page with names, but no student ID numbers
- for each part include:
- Assumptions made
- Legible schematics, diagrams, tables, etc. as required (each
page has to explain its self)
- A brief written summary of the results and the work you did
to arrive at them
- annotate any simulations
- Remember that bonus questions are mainly for
entertainment. Don't attempt them if you're pressed for
time.
- Any feedback on how the lab went that could be helpful to your
instructor
Past handouts, etc. can be picked up from a box on the self
opposite ECERF room w2-063. Walk through ECE reception, jog
left and the shelves will be on your right.
Submissions will not normally be re-graded more than two weeks
after the first day these have been returned in class.
The following calculators are permitted for examinations in this
course: faculty approved programmable calculators, faculty
approved non-programmable calculators, slide rules, and
instructor approved abacuses (if used quietly). Programmable
calculators will probably offer little or no advantage over
non-programmable calculators. Students must not distract
other students during exams, so please turn off the calculator
beep.
The final examination aid
sheets must be in the student’s own handwriting (both
sides, no photocopies or printouts), may be no larger than 21.59
by 27.94 cm paper, and may contain any information.
Deferred examinations may contain multiple components (including
an oral component) as determined by instructor.
Students requiring specialized support should provide letters
from SSDS to the instructor in the first 2 weeks of lectures.
Credit may only be received for one of EE453, ECE553, EE483 and
EE653.
Grade Determination Method
In this course, raw marks will be calculated up until after the
final exam. The resulting overall percentage mark will then be
converted for each student to a letter grade. A standard
expected distribution of grades, which is provided by the Faculty of
Engineering, will be used as a rough guideline when mapping
overall marks to grades. Absolute merit of the work will also
be taken into consideration.
Code of Student Behaviour
The University of Alberta is committed to the highest standards of
academic integrity and honesty. Students are expected to be familiar
with these standards regarding academic honesty and to uphold the
policies of the University in this respect. Students are
particularly urged to familiarize themselves with the provisions of
the Code of Student Behavior (online at http://www.ualberta.ca/secretariat/appeals.htm
) and avoid any behavior that could potentially result in suspicions
of cheating, plagiarism, misrepresentation of facts and/or
participation in an offence. Academic dishonesty is a serious
offence and can result in suspension or expulsion from the
University.
Policy about course outlines can be found in §23.4(2) of the
University Calendar.
Project
Design a significant integrated circuit and verify its functionality
and performance pin-to-pin simulation. Your design must
contain a full-custom portion and must contain some digital
circuits.
Present your work and results in a 10-20 minute seminar plus
questions. Bring a USB memory key with a PDF or PPT
presentation, or your own laptop. In this short presentation
time, give an overview of the application of your chip, the chip's
overall performance, and then descend into a few details where you
employed clever tricks, found some interesting tradeoffs, or
otherwise have a chance to teach your fellow designers something
interesting.
The main part of final report will be in the form of a
well-written 3-8 page "IEEE
2-column format paper" with embedded figures [LaTeX
style file, word
template]. (See me if you want to use a different
format.) In your abstract and introduction, clearly describe
what you achieved. Devote approximately a column to background
and past work, with references to the literature. Properly
quote and reference text and figures from other sources.
Describe analysis, simulations and, if applicable, selection between
design alternatives. Discuss speed-power-area tradeoffs.
Compare standard cell to full custom implementations if
applicable. Include block diagrams, schematics and layouts
(including full chip and custom blocks). In a box, summarize:
IC process
Dimensions
Power supply voltages and power
Clock frequency
Throughput
Circuit families used
Summarize number of pins used for what purpose and total (e.g.
Vdd/Vss-core, Vdd/Vss-IO, data in, data out, control)
Your report may contain any number of pages of appendix in any
format. Include as applicable:
index to appendices
VHDL/Verilog code, commented and human readable
Each page must have a title or enough information for me to figure
out what I'm looking at.
hierarchical schematics, if applicable
custom and chip layouts, hierarchical if applicable
annotated simulations, hierarchical if applicable
other verification: evidence (i.e. summaries, without killing too
many trees) of DRC, LVS, static timing
Library Resources
Textbook
CMOS VLSI Design - A Circuits and Design Perspective, 4rd Edition
N.H.E. Weste & D. Harris
Addison-Wesley 2011
http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html
including selected problem solutions
Lecture Notes
The most important material will be covered on the white
board. Please ensure you have a complete set of notes.
Selected lecture notes will be made
available online one week after the lecture. A
preliminary version may be available beforehand.
Use your ccic (Campus
Computer ID) to access course materials.
Labs
Use your ccid (Campus
Computer ID) to access course materials.
Lab
#
|
Lab
Dates
|
Report Due Date
|
0
|
Jan 10, 17
|
Jan 23
|
1
|
Jan 17, 31
|
Feb 6
|
2
|
Feb 14,
Mar 6
|
Mar 12
|
3
|
Mar 6, 20,
Apr 3
|
Apr 9
|
| Project
|
Mar 6, 20,
Apr 3, 10
|
Apr 13
|
Term Work
updated ~weekly
Manufacturer's Information