-- **********************************************************************
-- Filename: block_ram_toplevel.vhd
-- Authors: Ram S., Maziyar K., Yongjie L., Rejean L.
-- Date: Dec 7, 2004
--
-- Description: toplevel for coregen generated block ram module (with EN set)
--
-- NOTES: Must refer to this site to make CoreGen work - This will solve
-- the "HDLParsers:164" Error.
-- http://support.xilinx.com/xlnx/xil_ans_display.jsp?
-- iLanguageID=1&iCountryID=1&getPagePath=19221
-- **********************************************************************

library IEEE; 
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_signed.all;


ENTITY block_ram_entity_name IS
PORT (
	addr: IN std_logic_VECTOR(6 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(63 downto 0);
	dout: OUT std_logic_VECTOR(63 downto 0);
	en: IN std_logic;
	we: IN std_logic
	);
END block_ram_entity_name;

ARCHITECTURE rtl OF block_ram_entity_name IS

ATTRIBUTE box_type: STRING;


COMPONENT coregen_block_ram_component_name
	port (
	addr: IN std_logic_VECTOR(6 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(63 downto 0);
	dout: OUT std_logic_VECTOR(63 downto 0);
	en: IN std_logic;
	we: IN std_logic
	);
END COMPONENT;

ATTRIBUTE box_type OF coregen_block_ram_component_name : COMPONENT IS "black_box";

BEGIN

get_info : coregen_block_ram_component_name 
	PORT MAP (
	    addr => addr,
		clk => clk,
		din => din,
		dout => dout,
		en => en,
		we => we
	);
	
END rtl;