By: Ramkrishna Swamy, Maziyar Khorasani, Yongjie Liu, Rejean Lau
The Xilinx Virtex II Multimedia board provides 5 banks of external ZBT (Zero Bus Turnaround) SRAM. The actual choice of having a ZBT SRAM on the multimedia board has several advantages and disadvantages, depending on specific user requirements. The ZBT SRAM provides interleaved Read/Write without wasteful turnaround cycles, this is implemented in two ways pipelining and Flowthrough.
ZBT SRAM is a synchronous form of SRAM, however it provides maximum system throughput by making use of every bus cycle (unlike conventional SRAMs). This is achieved by eliminating turnaround cycles (ie. the cycles required when switching from read and write cycles) as demonstrated in Figure 1 below.
Furthermore, ZBT SRAM devices, as mentioned earlier have two main varieties, the pipelined method (which operates at a higher frequency), and a flowthrough method (which has shorter latency).
Through the LogiCORE module, a Single-Port Block Memory can be generated. This on FPGA memory supports all three Virtex-II write mode options: Read-After-Write, Read-Before-Write and No-Read-On-Write. Also it supports memory depths ranging up to 1M words for Virtex-II. The core is delivered through the Xilinx CORE Generator System and below; the process to integrate it into your design and to use all of its many useful functions is outlined.
There are several advantages to use the internal Block memory available, rather then external memory. By using internal memory, especially a core as in this case, the data can be statically loaded during programming. The data can be loaded by indicating a specific COE file during the module generation (more on this later). This is very useful for testing purposes, and it simplifies the working with memory process since no external signals (i.e. pins from outside the FPGA) have to be referenced.
For this design, the pipelined method of ZBT SRAM was chosen and thus the top level entity employed, and information that follows is regards to pipelined ZBT SRAM.
Pipelined ZBT SRAM
In pipelined ZBT SRAM, as can be seen from the below diagram, in Figure 2, the ZBT SRAM are late-late-read and late-late-write RAMs. During the read operation, valid data appears 2 clock cycles after the address and the control signals. Thus, the initial data takes two clock cycles, but every data following that is output (or input) on every successive clock signal.
Thus, again, to emphasis, on a write operation, the data needs to be inputted 2 clock cycles after the address and the control signals are registered.
Using the ZBT_TOP_LEVEL entity provided to instantiate a single bank of ZBT SRAM:
With this app note, there are two other files provided. One is the compressed file containing the source code of the Xilinx ZBT SRAM controller and CLOCKGEN design example, with the additional ZBT_TOP_LEVEL.vhd controller created for the purposes of this app note. The other file provided is simply the PDF data sheet for the ZBT SRAM used on the Xilinx Virtex II Multimedia Board. The links are provided below:
The two files should be all that is required to set up your ZBT SRAM and get your work started. First a bit of a description of the top level entity provided.
The ZBT_TOP_LEVEL.vhd file provided is simply a test program that can be used as a framework for developing your own ZBT SRAM controller. A limitation that was found with the board was that it only had two main I/O leds available for ease of use. Now in terms of debugging purposes, that is generally not sufficient. However, we found for that for simple tests, the 2 I/O leds are a bit crude but workable. To understand this controller though, you must first understand the two components instantiated in this design for correct functionality.
The ZBT_TOP_LEVEL.vhd module instantiates two VERILOG Design examples provided by Xilinx, the CLOCKGEN module and the ZBT Controller design example for one memory bank (MEMORY BANK 0) of ZBT SRAM. The CLOCKGEN module is simply used to provide the required clock to the ZBT SRAM. The ZBT SRAM design example is the the top level controller that provides the communication medium to the ZBT SRAM (however, as it was a bit more complicated to work with, the ZBT_TOP_LEVEL.vhd controller was written).
The clock used in this example is the CLOCKGEN module generated 108 Mhz memory clock. Taking this into account then, initially in the ZBT_TOP_LEVEL.vhd code, we delay for 1 second (ie. 100,000,000 cycles) and initialize the ZBT SRAM. It is important to note that large values where chosen such that specific changes of the LEDs lines would be visible to the human eye. Secondly, a write occurs 10 seconds (1000,000,000 cycles) later. This 'write' then writes an arbitrary value to the ZBT SRAM at address 0. The write is enabled by setting the user_memory_bank0_write to '1', and the user_memory_bank0_read to '0'. Then, by continually checking/reading that address that was just written to, we can then verify whether the write (and thus read) was successful or not by lighting up the Active LOW led so the human observer can see. Basically, this is the entire function of the ZBT_TOP_LEVEL.vhd file, it simply tests a single memory write and single memory read - a simple, but effective test to ensure functional memory and memory control.
Important Control Signals:
Now, if the provided ZBT_TOP_LEVEL.vhd is used, the only signals that are of importance are the signals listed below:
user_memory_bank0_write
- set to '1' to enable a write, '0' to disable writes
user_memory_bank0_read
- set to '1' to enable a read, '0' to disable reads
user_memory_bank0_write_data
- data to be written to the ZBT SRAM during a write operation
user_memory_bank0_read_data - data
read from the ZBT SRAM during a read operation
user_memory_bank0_addr
- the address to read/write from
These signals then are all that is needed for simple reads and writes to and from the ZBT SRAM. Further signals have been hard wired in the ZBT_TOP_LEVEL.vhd, but can also be wired up for further control.
Instantiating Multiple ZBT SRAM Banks:
The Xilinx II Multimedia board has 5 available banks of ZBT SRAM (banks 0, 1, 2, 3, 4). Using the basic ideas discussed here, all 5 banks can then be accessed for read/writes. To simply access any number of the 5 banks, the pin mappings for the banks need to be passed to the controller through the UCF file, and the proper signals mapped to the proper pins, besides mapping a lot of pins to a lot of wires, it is a simple operation.
Additional Links:
[1] Xilinx Virtex II Multimedia board main webpage (with links to the design examples): http://www.xilinx.com/products/boards/multimedia/
[2] Xilinx Synthesizable 200 MHz ZBT SRAM Interface app note (XAPP 136): http://www.xilinx.com/bvdocs/appnotes/xapp136.pdf