-- **********************************************************************
-- Filename: get_ram_data24_256.vhd
-- Authors:	Ram S., Maziyar K., Yongjie L., Rejean L.
-- Date:
--
-- Description:
--  Instantiates the RGB buffer block ram. Requires a 24 x 256 Block
--  single port RAM generated as an ipcore.

-- **********************************************************************

library IEEE; 
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_signed.all;


ENTITY get_ram_data24_256 IS
PORT (
	addr: IN std_logic_VECTOR(7 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(23 downto 0);
	dout: OUT std_logic_VECTOR(23 downto 0);
	en: IN std_logic;
	we: IN std_logic
	);
END get_ram_data24_256;

ARCHITECTURE rtl OF get_ram_data24_256 IS

ATTRIBUTE box_type: STRING;


COMPONENT block_ram_24_256
	port (
	addr: IN std_logic_VECTOR(7 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(23 downto 0);
	dout: OUT std_logic_VECTOR(23 downto 0);
	en: IN std_logic;
	we: IN std_logic
	);
END COMPONENT;

ATTRIBUTE box_type OF block_ram_24_256 : COMPONENT IS "black_box";



BEGIN

get_info : block_ram_24_256 
	PORT MAP (
	    addr => addr,
		clk => clk,
		din => din,
		dout => dout,
		en => en,
		we => we
	);
	
END rtl;ÿÿ