Filename: VGA_Control.vhd
Authors: Ram S., Maziyar K., Yongjie L., Rejean L.
Date: Dec 5

Description: Top level for the VGA controller. Creates the VGA synch 
signals from the SVGA_TIMING_GENERATION signals on reset. Needs an input signal
RGB_Data_Ready that starts the SVGA_TIMING_GENERATION address counter.

The low level synch information is provided in SVGADEFINES.v 
file, however two counters in the VGA_Control provides user control of pixels, 
and a level of abstraction which is easier to use. They are called vpixl_counter
and hpixl_counter respectively.


The files are set for a resolution of 600 x 800 for 
a 50 Mhz pixel clock, however, these parameters can be easily modified by
commenting out the information in SVGADEFINES.v and redefining the two
parameters in package defined at the top of VGA_Control.vhd, HORIZONTAL_MAX
and VERTICAL_MAX respectively.

The RGB buffer in this case uses a 256 (deep) x 24 bit (wide) single port block
ram which is to be generated through the Xilinx Core gen tools. It is programmed
to store 256 pixels for a 16 x 16 pixel image. The rgb.coe file needs to be initialized 
in the file, so that an image can be seen.


This program demonstrates usage of the counters by drawing frame borders at the top
and left of the screen, and places the 16 x 16 pixel image on the top left
screen (upside down smiley face).