--/*************************************************************************
--  
-- Filename: YCbCr_RGB_converter_tb.vhd
-- 
-- Author: Rejean Lau
   
    
-- Description: This is a testbench which implements 3 test cases to test
--              the conversion formulas for 8 bit Y,Cb,Cr inputs


-- Test 1 Input: Y'=16, Cb,Cr=128 (0)    Output: R,G,B should be 0

-- Test 2 Input: Y'=235, Cb,Cr=240	 
	--Output:R = 433.668 (overflow - output should be all 1's), 
	-- 	    G = 119.956 
	--	    B = 480.82 (overflow - output should be all 1's)

-- Test 3 Input: Y',Cb,Cr = 16   Output: R,B should be 0 because of the 
							--    negative sign bit test
						 	--    G should be 134

-- ***************************************************************************/

LIBRARY ieee,work;

USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE bench_behavioral OF testbench IS 

	COMPONENT ycrcb2rgb
	PORT(-- 8 bit values 
		Y,Cr,Cb : in std_logic_vector(7 downto 0); 
          clk,rst : in std_logic;
          R,G,B : out std_logic_vector(7 downto 0)
		
		-- 10 bit values
	     --Y,Cr,Cb : in std_logic_vector(9 downto 0); 
          --clk,rst : in std_logic;
         -- R,G,B : out std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	SIGNAL reset :  std_logic;
	SIGNAL sys_clk : std_logic;
	
	-- 8 bit signal input values
	SIGNAL Y :  std_logic_vector(7 downto 0);
	SIGNAL Cr :  std_logic_vector(7 downto 0);
	SIGNAL Cb :  std_logic_vector(7 downto 0);
	
	-- 10 bit signal input values
	--SIGNAL Y :  std_logic_vector(9 downto 0);
	--SIGNAL Cr :  std_logic_vector(9 downto 0);
	--SIGNAL Cb :  std_logic_vector(9 downto 0);


	SIGNAL R :  std_logic_vector(7 downto 0);
	SIGNAL G :  std_logic_vector(7 downto 0);
	SIGNAL B :  std_logic_vector(7 downto 0);



constant Tpw_clock : time := 50 ns;

BEGIN

	dut: ycrcb2rgb  PORT MAP(
		Y => Y,
		Cr => Cr,
		Cb => Cb,
		clk => sys_clk,
		rst => reset,
		R => R,
		G => G,
		B => B		
		);

	clock_gen : process is
	begin
		sys_clk<='1' after Tpw_clock,'0' after 2*Tpw_clock;
		wait for 2 * Tpw_clock;
	end process clock_gen;

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
          wait until sys_clk='1';
		reset <= '1';
		wait until sys_clk='1';
		reset <= '0';
	   
		wait until sys_clk='1';
		--Test #1    Input: Y'=16, Cb,Cr=128 (0)    Output: R,G,B should be 0
		
		--for 10 bit input
		--Y  <= "0001000000";
		--Cr <= "1000000000";
		--Cb <= "1000000000";

		--for 8 bit input
		   Y  <= "00010000";
		   Cr <= "10000000";
		   Cb <= "10000000";

		wait until sys_clk='1';

		--Test #2    Input: Y'=235, Cb,Cr=240	 Output: R = 433.668, G = 119.956, B = 480.82 
											-- R,B should be all ones because of overflow
		--for 10 bit input
		--Y  <= "1110101100";
		--Cr <= "1111000000";
		--Cb <= "1111000000";

		--for 8 bit input
		Y  <= "11101011";
		Cr <= "11110000";
		Cb <= "11110000";

		wait until sys_clk='1';

		--Test #3   Input: Y',Cb,Cr = 16   Ouput: R,B should be 0 because of the negative sign bit test
									  --   G should be 134
		--for 10 bit input
		--Y <=  "0001000000";
		--Cr <= "0001000000";
		--Cb <= "0001000000";

		--for 8 bit input
		Y <= "00010000";
		Cr <= "00010000";
		Cb <= "00010000";


	    	loop
			wait until sys_clk = '1';
		end loop;


   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;