The next Computer Architecture Seminar will discuss the following paper 
on Tuesday, Oct. 15 at 9:30am in CME 345:

THE RAW MICROPROCESSOR: A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND 
GENERAL-PURPOSE PROGRAMS.
Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat, F.; Greenwald, 
B.; Hoffman, H.; Johnson, P.; Jae-Wook Lee; Lee, W.; Ma, A.; Saraf, A.; 
Seneski, M.; Shnidman, N.; Strumpen, V.; Frank, M.; Amarasinghe, S.; 
Agarwal, A.
IEEE Micro , Volume: 22 Issue: 2 , March-April 2002 pp. 25-35

This paper is located at:
http://www.ee.ualberta.ca/~elliott/ee710/seminars/2002f/2002-10-15/Raw.pdf

ABSTRACT:
WIRE DELAY IS EMERGING AS THE NATURAL LIMITER TO MICROPROCESSOR
SCALABILITY. A NEW ARCHITECTURAL APPROACH COULD SOLVE THIS
PROBLEM, AS WELL AS DELIVER UNPRECEDENTED PERFORMANCE, ENERGY
EFFICIENCY, AND COST EFFECTIVENESS.

Further Information:
The Raw research prototype uses a scalable instruction set architecture 
(ISA) to attack the emerging wire-delay problem by providing a parallel, 
software interface to the gate, wire, and pin resources of the chip. An 
architecture that has direct, first-class analogs to all of these 
physical resources will ultimately let programmers achieve the maximum 
amount of performance.