The Computer Architecture Discussion Group will discuss one paper on Tuesday, Oct.08, CME 345, 9:30. You can find paper at: http://www.ee.ualberta.ca/~elliott/ee710/seminars/2002f/2002-10-08/ The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays ABSTRACT Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper pipelines. From our study of the SPEC 2000 benchmarks, we find that for a high-performance architecture implemented in 100nm technology, the optimal clock period is approximately 8 fan-out-of-four (FO4) inverter delays for integer benchmarks, comprised of 6 FO4 of useful work and an overhead of about 2 FO4. The optimal clock period for floating-point benchmarks is 6 FO4. We find these optimal points to be insensitive to latch and clock skew overheads. Our study indicates that further pipelining can at best improve performance of integer programs by a factor of 2 over current designs. At these high clock frequencies it will be difficult to design the instruction issue window to operate in a single cycle. Consequently, we propose and evaluate a high-frequency design called a segmented instruction window. International Conference on Computer Architecture (2002) SESSION: Session 1: Processor pipelines Authors M. S. Hrishikesh The University of Texas, Austin Doug Burger The University of Texas, Austin Norman P. Jouppi Compaq Computer Corporation Stephen W. Keckler The University of Texas, Austin Keith I. Farkas Compaq Computer Corporation Premkishore Shivakumar The University of Texas, Austin Sponsors SIGARCH : ACM Special Interest Group on Computer Architecture IEEE TCCA : IEEE Computer Society Technical Committee on Computer Architecture Publisher IEEE Computer Society Washington, DC, USA Pages: 14 - 24 Series-Proceeding-Section-Article Year of Publication: 2002 ISBN ~ ISSN:1063-6897 , 0-7695-1605-X regards -- Lei ZHU, MENG Dept. of Electrical and Computer Engineering University of Alberta zhulei@ee.ualberta.ca Edmonton, AB, Canada T6G 2V4