The Computer Architecture Discussion Group will meet 
selected Tuesdays, CME 345, 9:30
Next meeting Sept. 24.

All are invited to attend the whole series, or just the papers that catch your imagination.  This discussion group is held in conjunction
with EE710 Computer Architecture.  http://www.ee.ualberta.ca/~elliott/ee710/ 

Discussion leaders will make an informal 30 minute presentation of the main work in a paper, including a critique.  Then, everyone will jump
in with their thoughts on the paper.  Leaders can search for their own favourite or pick a paper on Computer Architecture from my list. 

People are also welcome to use this forum to get feedback on their presentations prior to conferences. 

Please let me know if you'ld like to schedule a slot as discussion leader.  Email list changes can also be directed to me.

You can find this week's paper in:
http://www.ee.ualberta.ca/~elliott/ee710/seminars/2002f/2002-9-24/


   Design tradeoffs for the Alpha EV8 conditional branch predictor 

      ABSTRACT 

    This paper presents the Alpha EV8 conditional branch predictor The Alpha EV8
    microprocessor project, canceled in June 2001 in a late phase of development,
    envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture
    featuring a very deep pipeline and simultaneous multithreading. Performance of
    such a processor is highly dependent on the accuracy of its branch predictor and
    consequently a very large silicon area was devoted to branch prediction on EV8. The
    Alpha EV8 branch predictor relies on global history and features a total of 352
    Kbits.The focus of this paper is on the different trade-offs performed to overcome
    various implementation constraints for the EV8 branch predictor. One such instance
    is the pipelining of the predictor on two cycles to facilitate the prediction of up to
    16 branches per cycle from any two dynamically successive, 8 instruction fetch
    blocks. This resulted in the use of three fetch-block old compressed branch history
    information for accesing the predictor. Implementation constraints also restricted
    the composition of the index functions for the predictor and forced the usage of only
    single-ported memory cells.Nevertheless, we show that the Alpha EV8 branch
    predictor achieves prediction accuracy in the same range as the state-of-the-art
    academic global history branch predictors that do not consider implementation
    constraints in great detail. 

ACM SIGARCH Computer Architecture News
   Volume 30 ,  Issue 2  (May 2002)
   SESSION: Session 9: Supporting deep speculation


   Authors 
     André Seznec  IRISA/INRIA, Campus de Beaulieu, 35042 Rennes, France 
     Stephen Felix  Intel, Shrewsbury, MA 
     Venkata Krishnan  StarGen, Inc., Marlborough, MA 
     Yiannakis Sazeides  University of Cyprus, CY-1678 Nicosia, Cyprus 

     Pages: 295 - 306
        http://doi.acm.org/10.1145/545214.545249         pdf 1.24 MB