# do capstone_main_run_msim_gate_vhdl.do 
# if {[file exists gate_work]} {
# 	vdel -lib gate_work -all
# }
# vlib gate_work
# vmap work gate_work
# Copying /opt/altera/10.1sp1/modelsim_ase/linux/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied /opt/altera/10.1sp1/modelsim_ase/linux/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vcom -93 -work work {capstone_main.vho}
# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov  2 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vital_primitives
# -- Loading package cycloneii_atom_pack
# -- Loading package cycloneii_components
# -- Compiling entity capstone_main
# -- Compiling architecture structure of capstone_main
# 
vsim gate_work.capstone_main
# vsim gate_work.capstone_main 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading cycloneii.cycloneii_atom_pack(body)
# Loading cycloneii.cycloneii_components
# Loading gate_work.capstone_main(structure)
# Loading cycloneii.cycloneii_pllpack(body)
# Loading cycloneii.cycloneii_pll(vital_pll)
# Loading cycloneii.cycloneii_m_cntr(behave)
# Loading cycloneii.cycloneii_n_cntr(behave)
# Loading cycloneii.cycloneii_scale_cntr(behave)
# Loading cycloneii.cycloneii_lcell_ff(vital_lcell_ff)
# Loading cycloneii.cycloneii_and1(altvital)
# Loading cycloneii.cycloneii_lcell_comb(vital_lcell_comb)
# Loading cycloneii.cycloneii_ram_block(block_arch)
# Loading cycloneii.cycloneii_ram_register(reg_arch)
# Loading cycloneii.cycloneii_ram_pulse_generator(pgen_arch)
# Loading cycloneii.cycloneii_jtag(architecture_jtag)
# Loading cycloneii.cycloneii_clkctrl(vital_clkctrl)
# Loading cycloneii.cycloneii_ena_reg(behave)
# Loading ieee.std_logic_arith(body)
# Loading cycloneii.cycloneii_io(structure)
# Loading cycloneii.cycloneii_mux21(altvital)
# Loading cycloneii.cycloneii_dffe(behave)
# Loading cycloneii.cycloneii_asynch_io(behave)
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tdo has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tmsutap has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tckutap has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tdiutap has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# Load canceled
find drivers -source -cause sim:/capstone_main/dram_ba_0
wave create -driver expectedOutput -pattern clock -initialvalue U -period 100ps -dutycycle 50 -starttime 0ps -endtime 1000ps sim:/capstone_main/dram_ba_0
# capstone_main
force -freeze sim:/capstone_main/clock_50 1 0, 0 {25 ps} -r 50
add wave \
{sim:/capstone_main/clock_50 } 
force -freeze sim:/capstone_main/clock_50 1 0, 0 {50 ps} -r 100
force -freeze sim:/capstone_main/clock_27 1 0, 0 {13 ps} -r 27
add wave \
{sim:/capstone_main/clock_27 } 
vsim work.capstone_main
# vsim work.capstone_main 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading cycloneii.cycloneii_atom_pack(body)
# Loading cycloneii.cycloneii_components
# Loading work.capstone_main(structure)
# Loading cycloneii.cycloneii_pllpack(body)
# Loading cycloneii.cycloneii_pll(vital_pll)
# Loading cycloneii.cycloneii_m_cntr(behave)
# Loading cycloneii.cycloneii_n_cntr(behave)
# Loading cycloneii.cycloneii_scale_cntr(behave)
# Loading cycloneii.cycloneii_lcell_ff(vital_lcell_ff)
# Loading cycloneii.cycloneii_and1(altvital)
# Loading cycloneii.cycloneii_lcell_comb(vital_lcell_comb)
# Loading cycloneii.cycloneii_ram_block(block_arch)
# Loading cycloneii.cycloneii_ram_register(reg_arch)
# Loading cycloneii.cycloneii_ram_pulse_generator(pgen_arch)
# Loading cycloneii.cycloneii_jtag(architecture_jtag)
# Loading cycloneii.cycloneii_clkctrl(vital_clkctrl)
# Loading cycloneii.cycloneii_ena_reg(behave)
# Loading ieee.std_logic_arith(body)
# Loading cycloneii.cycloneii_io(structure)
# Loading cycloneii.cycloneii_mux21(altvital)
# Loading cycloneii.cycloneii_dffe(behave)
# Loading cycloneii.cycloneii_asynch_io(behave)
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tdo has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tmsutap has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tckutap has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
# ** Warning: (vsim-8683) Uninitialized out port /capstone_main/altera_internal_jtag/tdiutap has no driver.
# This port will contribute value (U) to the signal network.
#         Region: /capstone_main
find drivers -source -cause sim:/capstone_main/clock_50
force -freeze sim:/capstone_main/clock_50 1 0, 0 {25 ps} -r 50
force -freeze sim:/capstone_main/clock_27 1 0, 0 {13 ps} -r 27
wave create -driver freeze -pattern clock -initialvalue 1 -period 100ps -dutycycle 50 -starttime 0ps -endtime 1000ps sim:/capstone_main/clock_50
# capstone_main
wave create -driver freeze -pattern clock -initialvalue 1 -period 100ps -dutycycle 27 -starttime 0ps -endtime 1000ps sim:/capstone_main/clock_27
# capstone_main
force -freeze Edit:/capstone_main/clock_27 1 0, 0 {13 ps} -r 27
# ** Error: (vsim-3561) No objects found matching 'Edit'.
# ** Error: (vsim-4008) Object 'Edit:/capstone_main/clock_27' not found.
# 
add wave \
{sim:/capstone_main/vga_clk } 
