---

clk_0

clock_source v10.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cpu_0

altera_nios2 v10.1

Parameters userDefinedSettings tightlyCoupledInstructionMaster3MapParam tightlyCoupledInstructionMaster3AddrWidth 1 tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledDataMaster3MapParam tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster0AddrWidth 1 setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave cfi_flash_0.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 3 instSlaveMapParam <address-map><slave name='cfi_flash_0.s1' start='0x400000' end='0x800000' /><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='sram_interface_0.sram' start='0x1080000' end='0x1100000' /><slave name='onchip_memory2_0.s1' start='0x1104000' end='0x1108000' /><slave name='cpu_0.jtag_debug_module' start='0x1108800' end='0x1109000' /></address-map> instAddrWidth 25 impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave onchip_memory2_0.s1 exceptionOffset 32 deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 deviceFamilyName Cyclone II debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false dataSlaveMapParam <address-map><slave name='cfi_flash_0.s1' start='0x400000' end='0x800000' /><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='sram_interface_0.sram' start='0x1080000' end='0x1100000' /><slave name='onchip_memory2_0.s1' start='0x1104000' end='0x1108000' /><slave name='cpu_0.jtag_debug_module' start='0x1108800' end='0x1109000' /><slave name='timer_0.s1' start='0x1109000' end='0x1109020' /><slave name='altpll_0.pll_slave' start='0x1109020' end='0x1109030' /><slave name='frame_addressing_0.frameaddr' start='0x1109030' end='0x1109040' /><slave name='sysid.control_slave' start='0x1109040' end='0x1109048' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1109048' end='0x1109050' /></address-map> dataAddrWidth 25 customInstSlavesSystemInfo <info/> cpuReset false cpuID 0 clockFrequency 50000000 breakSlave cpu_0.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 50000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 INITDA_SUPPORTED FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x1104020 RESET_ADDR 0x400000 BREAK_ADDR 0x1108820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 25 DATA_ADDR_WIDTH 25 NUM_OF_SHADOW_REG_SETS 0

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onchip_memory2_0

altera_avalon_onchip_memory2 v10.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 deviceFamily Cyclone II dualPort false initMemContent true initializationFileName onchip_memory2_0 instanceID NONE memorySize 16384 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "onchip_memory2_0" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 1 DUAL_PORT 0 SIZE_VALUE 16384u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

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sysid

altera_avalon_sysid v10.1

Parameters id 0 timestamp 1334083158 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 0u TIMESTAMP 1334083158u

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timer_0

altera_avalon_timer v10.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true systemFrequency 50000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 50000000u LOAD_VALUE 49999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

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jtag_uart_0

altera_avalon_jtag_uart v10.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_INPUT_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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altpll_0

altpll v10.1

Parameters HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit INTENDED_DEVICE_FAMILY Cyclone II WIDTH_CLOCK WIDTH_PHASECOUNTERSELECT PRIMARY_CLOCK INCLK0_INPUT_FREQUENCY 20000 INCLK1_INPUT_FREQUENCY OPERATION_MODE NORMAL PLL_TYPE QUALIFY_CONF_DONE COMPENSATE_CLOCK CLK0 SCAN_CHAIN GATE_LOCK_SIGNAL NO GATE_LOCK_COUNTER LOCK_HIGH LOCK_LOW VALID_LOCK_MULTIPLIER 1 INVALID_LOCK_MULTIPLIER 5 SWITCH_OVER_ON_LOSSCLK SWITCH_OVER_ON_GATED_LOCK ENABLE_SWITCH_OVER_COUNTER SKIP_VCO SWITCH_OVER_COUNTER SWITCH_OVER_TYPE FEEDBACK_SOURCE BANDWIDTH BANDWIDTH_TYPE SPREAD_FREQUENCY DOWN_SPREAD SELF_RESET_ON_GATED_LOSS_LOCK SELF_RESET_ON_LOSS_LOCK CLK0_MULTIPLY_BY 2 CLK1_MULTIPLY_BY 1 CLK2_MULTIPLY_BY 2 CLK3_MULTIPLY_BY CLK4_MULTIPLY_BY CLK5_MULTIPLY_BY CLK6_MULTIPLY_BY CLK7_MULTIPLY_BY CLK8_MULTIPLY_BY CLK9_MULTIPLY_BY EXTCLK0_MULTIPLY_BY EXTCLK1_MULTIPLY_BY EXTCLK2_MULTIPLY_BY EXTCLK3_MULTIPLY_BY CLK0_DIVIDE_BY 1 CLK1_DIVIDE_BY 2 CLK2_DIVIDE_BY 1 CLK3_DIVIDE_BY CLK4_DIVIDE_BY CLK5_DIVIDE_BY CLK6_DIVIDE_BY CLK7_DIVIDE_BY CLK8_DIVIDE_BY CLK9_DIVIDE_BY EXTCLK0_DIVIDE_BY EXTCLK1_DIVIDE_BY EXTCLK2_DIVIDE_BY EXTCLK3_DIVIDE_BY CLK0_PHASE_SHIFT -3000 CLK1_PHASE_SHIFT 0 CLK2_PHASE_SHIFT 0 CLK3_PHASE_SHIFT CLK4_PHASE_SHIFT CLK5_PHASE_SHIFT CLK6_PHASE_SHIFT CLK7_PHASE_SHIFT CLK8_PHASE_SHIFT CLK9_PHASE_SHIFT EXTCLK0_PHASE_SHIFT EXTCLK1_PHASE_SHIFT EXTCLK2_PHASE_SHIFT EXTCLK3_PHASE_SHIFT CLK0_DUTY_CYCLE 50 CLK1_DUTY_CYCLE 50 CLK2_DUTY_CYCLE 50 CLK3_DUTY_CYCLE CLK4_DUTY_CYCLE CLK5_DUTY_CYCLE CLK6_DUTY_CYCLE CLK7_DUTY_CYCLE CLK8_DUTY_CYCLE CLK9_DUTY_CYCLE EXTCLK0_DUTY_CYCLE EXTCLK1_DUTY_CYCLE EXTCLK2_DUTY_CYCLE EXTCLK3_DUTY_CYCLE PORT_clkena0 PORT_UNUSED PORT_clkena1 PORT_UNUSED PORT_clkena2 PORT_UNUSED PORT_clkena3 PORT_UNUSED PORT_clkena4 PORT_UNUSED PORT_clkena5 PORT_UNUSED PORT_extclkena0 PORT_extclkena1 PORT_extclkena2 PORT_extclkena3 PORT_extclk0 PORT_UNUSED PORT_extclk1 PORT_UNUSED PORT_extclk2 PORT_UNUSED PORT_extclk3 PORT_UNUSED PORT_CLKBAD0 PORT_UNUSED PORT_CLKBAD1 PORT_UNUSED PORT_clk0 PORT_USED PORT_clk1 PORT_USED PORT_clk2 PORT_USED PORT_clk3 PORT_UNUSED PORT_clk4 PORT_UNUSED PORT_clk5 PORT_UNUSED PORT_clk6 PORT_clk7 PORT_clk8 PORT_clk9 PORT_SCANDATA PORT_UNUSED PORT_SCANDATAOUT PORT_UNUSED PORT_SCANDONE PORT_UNUSED PORT_SCLKOUT1 PORT_SCLKOUT0 PORT_ACTIVECLOCK PORT_UNUSED PORT_CLKLOSS PORT_UNUSED PORT_INCLK1 PORT_UNUSED PORT_INCLK0 PORT_USED PORT_FBIN PORT_UNUSED PORT_PLLENA PORT_UNUSED PORT_CLKSWITCH PORT_UNUSED PORT_ARESET PORT_UNUSED PORT_PFDENA PORT_UNUSED PORT_SCANCLK PORT_UNUSED PORT_SCANACLR PORT_UNUSED PORT_SCANREAD PORT_UNUSED PORT_SCANWRITE PORT_UNUSED PORT_ENABLE0 PORT_ENABLE1 PORT_LOCKED PORT_UNUSED PORT_CONFIGUPDATE PORT_UNUSED PORT_FBOUT PORT_PHASEDONE PORT_UNUSED PORT_PHASESTEP PORT_UNUSED PORT_PHASEUPDOWN PORT_UNUSED PORT_SCANCLKENA PORT_UNUSED PORT_PHASECOUNTERSELECT PORT_UNUSED PORT_VCOOVERRANGE PORT_VCOUNDERRANGE DPA_MULTIPLY_BY DPA_DIVIDE_BY DPA_DIVIDER VCO_MULTIPLY_BY VCO_DIVIDE_BY SCLKOUT0_PHASE_SHIFT SCLKOUT1_PHASE_SHIFT VCO_FREQUENCY_CONTROL VCO_PHASE_SHIFT_STEP USING_FBMIMICBIDIR_PORT SCAN_CHAIN_MIF_FILE AVALON_USE_SEPARATE_SYSCLK NO HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 1 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#VALID_LOCK_MULTIPLIER 1 CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#CLK0_PHASE_SHIFT -3000 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#INVALID_LOCK_MULTIPLIER 5 CT#CLK2_MULTIPLY_BY 2 CT#INTENDED_DEVICE_FAMILY {Cyclone II} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#GATE_LOCK_SIGNAL NO CT#PORT_LOCKED PORT_UNUSED HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 1 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 0 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 1 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 0 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_ENA_CHECK 0 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 0 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 -3.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#BANDWIDTH_USE_CUSTOM 0 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 100.000000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 ns PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone II} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1331833166789414.mif PT#ACTIVECLK_CHECK 0 HIDDEN_USED_PORTS UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used HIDDEN_IS_NUMERIC IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#VALID_LOCK_MULTIPLIER 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#INVALID_LOCK_MULTIPLIER 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} HIDDEN_IS_FIRST_EDIT 0 AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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sdram_0

altera_avalon_new_sdram_controller v10.1

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 2 clockRate 50000000 columnWidth 8 dataWidth 16 generateSimulationModel false initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 12 size 8388608 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 0 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 22 SDRAM_ROW_WIDTH 12 SDRAM_COL_WIDTH 8 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 2 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

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tri_state_bridge_0

altera_avalon_tri_state_bridge v10.1

Parameters registerIncomingSignals true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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sram_interface_0

sram_interface v1.0

Parameters sharedPorts deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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read_from_memory_0

read_from_memory v1.0

Parameters AUTO_CLOCK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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write_to_memory_0

write_to_memory v1.0

Parameters AUTO_CLOCK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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frame_addressing_0

frame_addressing v1.0

Parameters AUTO_CLOCK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cfi_flash_0

altera_avalon_cfi_flash v10.1

Parameters actualHoldTime 40.0 actualSetupTime 40.0 actualWaitTime 140.0 addressWidth 22 clockRate 50000000 corePreset CUSTOM dataWidth 8 holdTime 40 setupTime 40 sharedPorts timingUnits NS waitTime 140 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments SETUP_VALUE 40 WAIT_VALUE 140 HOLD_VALUE 40 TIMING_UNITS "ns" SIZE 4194304u

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tri_state_bridge_1

altera_avalon_tri_state_bridge v10.1

Parameters registerIncomingSignals true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)