nios_system |

2012.04.11.15:19:30 | Datasheet

Overview

clk | nios_system
clk_27
| pio_0
| out_port
| out_port

Processor
CPU Nios II 11.1
All Components
CPU altera_nios2 11.1
JTAG_UART altera_avalon_jtag_uart 11.1
Interval_Timer altera_avalon_timer 11.1
sysid altera_avalon_sysid 11.1
SDRAM altera_avalon_new_sdram_controller 11.1
Red_LEDs altera_up_avalon_parallel_port 11.0
Green_LEDs altera_up_avalon_parallel_port 11.0
HEX3_HEX0 altera_up_avalon_parallel_port 11.0
HEX7_HEX4 altera_up_avalon_parallel_port 11.0
Slider_Switches altera_up_avalon_parallel_port 11.0
Pushbuttons altera_up_avalon_parallel_port 11.0
AV_Config altera_up_avalon_audio_and_video_config 11.0
Audio altera_up_avalon_audio 11.0
Char_LCD_16x2 altera_up_avalon_character_lcd 11.0
External_Clocks altera_up_avalon_clocks 11.0
pio_0 altera_avalon_pio 11.1
pio_1 altera_avalon_pio 11.1
tri_state_bridge_0 altera_avalon_tri_state_bridge 11.1
Memory Map

| CPU
instruction_master | data_master
CPU |  |
jtag_debug_module | 0x0a000000 | 0x0a000000
JTAG_UART |  |
avalon_jtag_slave |  | 0x10001000
Interval_Timer |  |
s1 |  | 0x10002000
sysid |  |
control_slave |  | 0x10002020
SDRAM |  |
s1 | 0x00000000 | 0x00000000
Red_LEDs |  |
avalon_parallel_port_slave |  | 0x10000000
Green_LEDs |  |
avalon_parallel_port_slave |  | 0x10000010
HEX3_HEX0 |  |
avalon_parallel_port_slave |  | 0x10000020
HEX7_HEX4 |  |
avalon_parallel_port_slave |  | 0x10000030
Slider_Switches |  |
avalon_parallel_port_slave |  | 0x10000040
Pushbuttons |  |
avalon_parallel_port_slave |  | 0x10000050
AV_Config |  |
avalon_av_config_slave |  | 0x10003000
Audio |  |
avalon_audio_slave |  | 0x10003040
Char_LCD_16x2 |  |
avalon_lcd_slave |  | 0x10003050
External_Clocks |  |
avalon_clocks_slave |  | 0x10002030
pio_0 |  |
s1 |  | 0x01000000
pio_1 |  |
s1 |  | 0x01000010
cfi_flash_0 |  |
s1 | 0x00c00000 | 0x00c00000

## clk

clock_source v11.1

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## CPU

altera_nios2 v11.1

External_Clocks | sys_clk | CPU
clk
|  | data_master | JTAG_UART
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | Interval_Timer
|  | s1
|  | d_irq
|  | irq
|  | data_master | sysid
|  | control_slave
|  | instruction_master | SDRAM
|  | s1
|  | data_master
|  | s1
|  | data_master | Red_LEDs
|  | avalon_parallel_port_slave
|  | data_master | Green_LEDs
|  | avalon_parallel_port_slave
|  | data_master | HEX3_HEX0
|  | avalon_parallel_port_slave
|  | data_master | HEX7_HEX4
|  | avalon_parallel_port_slave
|  | data_master | Slider_Switches
|  | avalon_parallel_port_slave
|  | data_master | Pushbuttons
|  | avalon_parallel_port_slave
|  | d_irq
|  | interrupt
|  | data_master | Audio
|  | avalon_audio_slave
|  | data_master
|  | avalon_audio_slave
|  | d_irq
|  | interrupt
|  | data_master | Char_LCD_16x2
|  | avalon_lcd_slave
|  | data_master | AV_Config
|  | avalon_av_config_slave
|  | custom_instruction_master | CPU_fpoint
|  | s1
|  | data_master | External_Clocks
|  | avalon_clocks_slave
|  | data_master | pio_0
|  | s1
|  | data_master | pio_1
|  | s1
|  | instruction_master | tri_state_bridge_0
|  | avalon_slave
|  | data_master
|  | avalon_slave

## Parameters
userDefinedSettings |
tightlyCoupledInstructionMaster3MapParam |
tightlyCoupledInstructionMaster3AddrWidth | 1
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledDataMaster3MapParam |
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster0AddrWidth | 1
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Static
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | cfi_flash_0.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | true
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _10
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
internalIrqMaskSystemInfo | 15
instSlaveMapParam | <address-map><slave name='SDRAM.s1' start='0x0' end='0x800000' /><slave name='cfi_flash_0.s1' start='0xC00000' end='0x1000000' /><slave name='CPU.jtag_debug_module' start='0xA000000' end='0xA000800' /></address-map>
instAddrWidth | 28
impl | Small
icache_size | _4096
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | SDRAM.s1
exceptionOffset | 32
deviceFeaturesSystemInfo | ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
deviceFamilyName | Cyclone II
debug_triggerArming | true
debug_level | Level2
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _4
dcache_bursts | false
dataSlaveMapParam | <address-map><slave name='SDRAM.s1' start='0x0' end='0x800000' /><slave name='cfi_flash_0.s1' start='0xC00000' end='0x1000000' /><slave name='pio_0.s1' start='0x1000000' end='0x1000010' /><slave name='pio_1.s1' start='0x1000010' end='0x1000020' /><slave name='CPU.jtag_debug_module' start='0xA000000' end='0xA000800' /><slave name='Red_LEDs.avalon_parallel_port_slave' start='0x10000000' end='0x10000010' /><slave name='Green_LEDs.avalon_parallel_port_slave' start='0x10000010' end='0x10000020' /><slave name='HEX3_HEX0.avalon_parallel_port_slave' start='0x10000020' end='0x10000030' /><slave name='HEX7_HEX4.avalon_parallel_port_slave' start='0x10000030' end='0x10000040' /><slave name='Slider_Switches.avalon_parallel_port_slave' start='0x10000040' end='0x10000050' /><slave name='Pushbuttons.avalon_parallel_port_slave' start='0x10000050' end='0x10000060' /><slave name='JTAG_UART.avalon_jtag_slave' start='0x10001000' end='0x10001008' /><slave name='Interval_Timer.s1' start='0x10002000' end='0x10002020' /><slave name='sysid.control_slave' start='0x10002020' end='0x10002028' /><slave name='External_Clocks.avalon_clocks_slave' start='0x10002030' end='0x10002032' /><slave name='AV_Config.avalon_av_config_slave' start='0x10003000' end='0x10003010' /><slave name='Audio.avalon_audio_slave' start='0x10003040' end='0x10003050' /><slave name='Audio.avalon_audio_slave' start='0x10003040' end='0x10003050' /><slave name='Char_LCD_16x2.avalon_lcd_slave' start='0x10003050' end='0x10003052' /></address-map>
dataAddrWidth | 29
customInstSlavesSystemInfo | <info><slave name="fpoint" baseAddress="252" addressSpan="4" clockCycleType="VARIABLE" /></info>
cpuReset | false
cpuID | 0
clockFrequency | 50000000
breakSlave | CPU.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
CPU_IMPLEMENTATION | "small"
BIG_ENDIAN | 0
CPU_FREQ | 50000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
DCACHE_LINE_SIZE | 0
DCACHE_LINE_SIZE_LOG2 | 0
DCACHE_SIZE | 0
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x20
RESET_ADDR | 0xc00000
BREAK_ADDR | 0xa000020
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 1
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 28
DATA_ADDR_WIDTH | 29

## JTAG_UART

altera_avalon_jtag_uart v11.1

CPU | data_master | JTAG_UART
avalon_jtag_slave
d_irq
irq
External_Clocks | sys_clk
clk

## Parameters
allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
WRITE_DEPTH | 64
READ_DEPTH | 64
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## Interval_Timer

altera_avalon_timer v11.1

CPU | data_master | Interval_Timer
s1
d_irq
irq
External_Clocks | sys_clk
clk

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 125.0
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 50000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 125.0
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 50000000u
LOAD_VALUE | 6249999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 8u

## sysid

altera_avalon_sysid v11.1

CPU | data_master | sysid
control_slave
External_Clocks | sys_clk
clk

## Parameters
id | 0
timestamp | 1334179130
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ID | 0u
TIMESTAMP | 1334179130u

## SDRAM

altera_avalon_new_sdram_controller v11.1

CPU | instruction_master | SDRAM
s1
data_master
s1
External_Clocks | sys_clk
clk

## Parameters
TAC | 5.5
TMRD | 3
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
clockRate | 50000000
columnWidth | 8
dataWidth | 16
generateSimulationModel | false
initNOPDelay | 0.0
initRefreshCommands | 2
masteredTristateBridgeSlave |
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 100.0
refreshPeriod | 15.625
registerDataIn | true
rowWidth | 12
size | 8388608
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
REGISTER_DATA_IN | 1
SIM_MODEL_BASE | 0
SDRAM_DATA_WIDTH | 16
SDRAM_ADDR_WIDTH | 22
SDRAM_ROW_WIDTH | 12
SDRAM_COL_WIDTH | 8
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_NUM_BANKS | 4
REFRESH_PERIOD | 15.625
POWERUP_DELAY | 100.0
CAS_LATENCY | 3
T_RFC | 70.0
T_RP | 20.0
T_MRD | 3
T_RCD | 20.0
T_AC | 5.5
T_WR | 14.0
INIT_REFRESH_COMMANDS | 2
INIT_NOP_DELAY | 0.0
SHARED_DATA | 0
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
IS_INITIALIZED | 1
SDRAM_BANK_WIDTH | 2
CONTENTS_INFO | ""

## Red_LEDs

altera_up_avalon_parallel_port v11.0

CPU | data_master | Red_LEDs
avalon_parallel_port_slave
External_Clocks | sys_clk
clock_reset

## Parameters
board | DE2
custom_port | false
preset | LEDs
leds | Red
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 18
direction | Output only
custom_DW | 32
custom_direction | Input only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## Green_LEDs

altera_up_avalon_parallel_port v11.0

CPU | data_master | Green_LEDs
avalon_parallel_port_slave
External_Clocks | sys_clk
clock_reset

## Parameters
board | DE2
custom_port | false
preset | LEDs
leds | Green
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 9
direction | Output only
custom_DW | 32
custom_direction | Input only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## HEX3_HEX0

altera_up_avalon_parallel_port v11.0

CPU | data_master | HEX3_HEX0
avalon_parallel_port_slave
External_Clocks | sys_clk
clock_reset

## Parameters
board | DE2
custom_port | false
preset | Seven Segment Displays
leds | Green
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 32
direction | Output only
custom_DW | 32
custom_direction | Input only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## HEX7_HEX4

altera_up_avalon_parallel_port v11.0

CPU | data_master | HEX7_HEX4
avalon_parallel_port_slave
External_Clocks | sys_clk
clock_reset

## Parameters
board | DE2
custom_port | false
preset | Seven Segment Displays
leds | Green
sevensegs | 7 to 4
gpio | GPIO 0 (JP1)
DW | 32
direction | Output only
custom_DW | 32
custom_direction | Input only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## Slider_Switches

altera_up_avalon_parallel_port v11.0

CPU | data_master | Slider_Switches
avalon_parallel_port_slave
External_Clocks | sys_clk
clock_reset

## Parameters
board | DE2
custom_port | false
preset | Slider Switches
leds | Green
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 18
direction | Input only
custom_DW | 32
custom_direction | Input only
capture | false
edge | Rising
irq | false
irq_type | Level
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## Pushbuttons

altera_up_avalon_parallel_port v11.0

CPU | data_master | Pushbuttons
avalon_parallel_port_slave
d_irq
interrupt
External_Clocks | sys_clk
clock_reset

## Parameters
board | DE2
custom_port | false
preset | Pushbuttons
leds | Green
sevensegs | 3 to 0
gpio | GPIO 0 (JP1)
DW | 4
direction | Input only
custom_DW | 32
custom_direction | Input only
capture | true
edge | Falling
irq | true
irq_type | Edge
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## AV_Config

altera_up_avalon_audio_and_video_config v11.0

CPU | data_master | AV_Config
avalon_av_config_slave
External_Clocks | sys_clk
clock_reset

## Parameters
device | On-Board Peripherals
board | DE2
eai | true
audio_in | Microphone to ADC
dac_enable | true
mic_bypass | false
line_in_bypass | true
mic_attenuation | -6dB
data_format | Left Justified
bit_length | 32
sampling_rate | 48 kHz
bosr | 250fs/256fs
sr_register | 0
video_format | NTSC
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## Audio

altera_up_avalon_audio v11.0

CPU | data_master | Audio
avalon_audio_slave
data_master
avalon_audio_slave
d_irq
interrupt
External_Clocks | sys_clk
clock_reset

## Parameters
audio_in | true
audio_out | true
dw | 32
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## Char_LCD_16x2

altera_up_avalon_character_lcd v11.0

CPU | data_master | Char_LCD_16x2
avalon_lcd_slave
External_Clocks | sys_clk
clock_reset

## Parameters
cursor | Both
AUTO_CLOCK_RESET_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## CPU_fpoint

altera_nios_custom_instr_floating_point v11.1

CPU | custom_instruction_master | CPU_fpoint
s1

## Parameters
useDivider | 1
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## clk_27

clock_source v11.1

## Parameters
clockFrequency | 27000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## External_Clocks

altera_up_avalon_clocks v11.0

clk | clk | External_Clocks
clk_in_primary
CPU | data_master
avalon_clocks_slave
clk_27 | clk
clk_in_secondary
|  | sys_clk | CPU
|  | clk
|  | sys_clk | SDRAM
|  | clk
|  | sys_clk | Red_LEDs
|  | clock_reset
|  | sys_clk | HEX3_HEX0
|  | clock_reset
|  | sys_clk | Green_LEDs
|  | clock_reset
|  | sys_clk | HEX7_HEX4
|  | clock_reset
|  | sys_clk | Slider_Switches
|  | clock_reset
|  | sys_clk | Pushbuttons
|  | clock_reset
|  | sys_clk | JTAG_UART
|  | clk
|  | sys_clk | Interval_Timer
|  | clk
|  | sys_clk | sysid
|  | clk
|  | sys_clk | AV_Config
|  | clock_reset
|  | sys_clk | Audio
|  | clock_reset
|  | sys_clk | Char_LCD_16x2
|  | clock_reset

## Parameters
board | DE2
sys_clk_freq | 50
sdram_clk | true
vga_clk | true
audio_clk | true
audio_clk_freq | 12.288
AUTO_CLK_IN_PRIMARY_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Cyclone II
deviceFamily | Cyclone II
generateLegacySim | false

## Software Assignments (none)

## pio_0

altera_avalon_pio v11.1

clk | clk | pio_0
clk
CPU | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 32
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## pio_1

altera_avalon_pio v11.1

clk | clk | pio_1
clk
CPU | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 32
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## cfi_flash_0

altera_avalon_cfi_flash v11.1

clk | clk | cfi_flash_0
clk
tri_state_bridge_0 | tristate_master
s1

## Parameters
actualHoldTime | 40.0
actualSetupTime | 40.0
actualWaitTime | 140.0
addressWidth | 22
clockRate | 50000000
corePreset | CUSTOM
dataWidth | 8
holdTime | 40
setupTime | 40
sharedPorts |
timingUnits | NS
waitTime | 140
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
SETUP_VALUE | 40
WAIT_VALUE | 140
HOLD_VALUE | 40
TIMING_UNITS | "ns"
SIZE | 4194304u

## tri_state_bridge_0

altera_avalon_tri_state_bridge v11.1

clk | clk | tri_state_bridge_0
clk
CPU | instruction_master
avalon_slave
data_master
avalon_slave
|  | tristate_master | cfi_flash_0
|  | s1

## Parameters
registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

generation took 0.01 seconds | rendering took 0.26 seconds