VHDL Coding Standards

•Use descriptive identifier names (not S0, S1, etc. for states)

–Pin names from manufacture’s datasheets and provided entities
(e.g. D(7 downto 0), Q, Cin ) may be acceptable

•Paragraph (indent) your code

–Break long lines (look at your printouts!)

–control the amount of indentation and size of tabs; small indents don’t rob you of space to put your code

–Use blank lines

•Use consistent capitalization

•Avoid "Magic Numbers" (numbers throughout your code)

–declare and use constants and generics so your code is portable and maintainable

•Put constant and component definitions in packages

–(saves typing too)

•Use hierarchy to your advantage

–reuse code

•-- Use comments --

–Start each file with a comment block, including entity names, author(s), date, project/lab, description

–Describe in general terms what each architecture or subprogram does

–Define non-obvious signals

–Explain tricky pieces of code

–Don’t hand in "commented out code"

•Use named association in port map’s

–e.g. port map ( clock => clock, d => stage1, q => stage2)

–(positional association is harder to debug)

•Use VHDL 93 syntax extensions

–make effective use of optional labels at end of entity, architecture, process

•Use vectors, arrays and other datastructures to simplify code

–(reduce code size, reduce human error, improve readability)