CMPE 490 -
Design of Microprocessor-based Systems
CMPE 450 -
Nanoscale System Design Project
Winter
Term (2012w) last updated 2012-1-24
Presentation Schedule TBD
Course web
page:
http://www.ece.ualberta.ca/~elliott/cmpe490/
Use the class
group to ask
questions, answer questions, etc.
Use email for
questions of a confidential nature or not applicable to anyone
else.
Instructor:
Please note that all email addresses are in the ualberta.ca domain
except where noted otherwise
Lab
Instructor and Stores Technician:
- Nancy Minderman
Office: ETLC 03-012
E-mail: Nancy.Minderman
- Rick McGregor
Office: ETLC 03-012
E-mail: rmcgreg
Teaching
Assistants:
- Pawel Pytlak
E-mail: ppytlak
- James Rodway
E-mail: jrodway
General Course Info
Lecture Section:
- Tuesday and Thursday 8 - 9 A.M. (Lectures will end before the
end of term)
GSB 211
Laboratory
Sections (ETLC 3-011):
|
|
Monday |
2 - 4:50 PM |
|
|
Wednesday |
2 - 4:50 PM |
Labs time
will be reorganized as needed.
You have
extended (building hours) access to the lab with your one-card.
Office hours
An Electrical and Computer Engineering computing account is
required in order to use the lab workstations. Students who have
forgotten their password should contact our IT support group in
ECERF W2-070
All information
pertinent to the laboratories and project is posted on the Laboratory
Page
Laboratory
sessions will be held in ETLC E3-011 and will include the
following scheduled labs:
- Laboratory #1 Worth 33% of the lab mark.
- Laboratory #2 Worth 33% of the lab mark.
- Laboratory #3 Worth 33% of the lab mark.
Consult the Laboratory page for a complete schedule.
Lab resources for labs and project.
Marking
Tentative
Marking scheme
Items [that
were] denoted with ?? are tentative and are to be decided by
majority vote in class by deadlines set by instructor.
Bonuses may
be available on some marked materials.
Past
handouts, etc. can be picked up from a box on the shelf opposite
ECERF room w2-065. Walk through ECE reception, jog left and
the shelves will be on your right.
Submissions will
not normally be re-graded more than two weeks after the first day
these have been returned in class.
Labs must be
demonstrated on time. Late project reports will be penalized
20% of the assigned mark per school day or part thereof.
Application of
group self-evaluation (division of marks), the dissolution or
reorganization of groups and sharing requirements between
former group members will be at the instructor's discretion.
The minutes of weekly group meetings could significantly impact
the outcome.
Students
requiring specialized support should provide letters from SSDS to the
instructor in the first 2 weeks of lectures.
Project
In groups of
2 or 3 (depending on scope of project) students will specify,
design and implement an embedded system.
Project
reports provided as PDF files must be electronically
submitted to your instructor by 6pm on the due date.
You may
change your goals during the term. Marking will be based on
what you achieve. Set basic goals and keep a list of
features to add once the basic functionality is achieved.
The
requirements for each project report can
be found here.
Ideas for the
project can
be found here. Having a client for your project is
optional this year. You may propose your own project and be
your own client.
Any variation
from the requirements, below, require approval of your instructor:
- You need permission to use a platform other than the Altera
DE2. In any event, a demonstration on the DE2 board is
recommended should your other platform fail.
- Your design must have elements of software and hardware
design. Interfacing hardware via the processor bus
(including within the FPGA) or via a co-processor interface is
encouraged.
- Your embedded system must start on power up
(program/configuration in flash memory, not downloaded).
- Reuse of design components is encouraged. Be sure to
cite other people's work, application notes, etc.
- Robust mechanical design is expected. Don't use the
white bread boards for the final project. Use connectors
and cables rather than loose wires. Reports of "It was
working last night", although invariably true, will be met with
limited sympathy.
CMPE 450 students have the
following additional requirements:
- Part of the project should include hardware design using an
FPGA.
- The VHDL (or Verilog) used in the FPGA design should be used
to design and verify an integrated circuit design. You
will be shown how to do this in EE 453.
Students in CMPE 490 can also create such a chip design as part
of their projects.
Grade
Determination Method
In this
course, a raw mark will be calculated from all graded course
components. The resulting overall percentage mark will then
be converted for each student to a letter grade. A standard
expected distribution of grades, which is provided by the Faculty
of Engineering, will be used as a rough guideline when mapping overall marks
to grades. Absolute merit of the work will be taken into
consideration.
Code of Student
Behaviour
The
University of Alberta is committed to the highest standards of
academic integrity and honesty. Students are expected to be
familiar with these standards regarding academic honesty and to
uphold the policies of the University in this respect. Students
are particularly urged to familiarize themselves with the
provisions of the Code of Student Behavior (online at http://www.ualberta.ca/secretariat/appeals.htm ) and avoid any
behavior that could potentially result in suspicions of cheating,
plagiarism, misrepresentation of facts and/or participation in an
offence. Academic dishonesty is a serious offence and can result
in suspension or expulsion from the University.
Policy about
course outlines can be found in §23.4(2) of the University
Calendar.
Lecture Notes
The most
important material will be covered on the white board.
Please ensure you have a complete set of notes.
Selected
lecture notes will be made
available online one week after the lecture. A
preliminary version may be available beforehand. Some slides
are courtesy of Altera and other manufacturers.
Use your ccic (Campus Computer ID) to access course
materials.