Introduction

Clock_divide is a module that will allow the dividing of any clock through the use of a carry-save counter rather than using a counter that is implemented using ripple-carry. With Clock_divide, you can take any input clock and divide it to suit your needs. When using this method for a clock divider, you receive a total clock with the period and frequency you desire. When running timing analyzer on this implementation the maximum frequency is ~50MHz which is well above the current capabilities of the ALTERA, which has a system clock around 25MHz.

Features

• can specify the carry-save values that are waiting for. (i.e. if want to divide by 10, part1 = 1 and part2 = 4)
• can input any clock and get a fully functional output clock of ~ the frequency that is desired
• a C program was developed to help the user find the values that they need for the counter parts

Author

clock_divide was written by Daniel Leder, a member of the Porta-Amp team. You are welcome to email any questions, comments, or suggestions to the author.

Testing and suggestions were provided by the rest of the Porta-Amp team: Kevin Mlazgar, John Koob, Danny Islam, and Edmund Fung.