EE 651 - Digital System Testing and Design for Testability

January - April, 2000

Problem Set #1

  1. Briefly explain why ICs, PCBs and systems need to be tested.
  2. What is the difference between design verification and production testing?
  3. Test vectors are commonly developed during design verification (and they are often re-used during production testing). Why are additional vectors usually required in a production test as compared to a design verification test?
  4. What is the ``rule of 10s'' and what are its main consequences for testing?
  5. What is the ``bathtub curve'' and what are the consequences for semiconductor testing?
  6. What is meant by the terms ``wafer probe'', ``production test'', ``burn-in'', ``incoming inspection'', ``on-line testing'', and ``off-line testing'', ``fault diagnosis''? How would the corresponding tests differ, if at all?
  7. What are the three main kinds of tests within a typical IC production test?
  8. Define the terms ``physical defect'', ``failure mechanism'', ``failure'', ``error'', and ``fault''?
  9. What are the advantages and disadvantages of using a fault model? What are the limitations of testing without a fault model?
  10. What are some of the more common physical defects that occur in ICs?
  11. What are some of the failure mechanisms that cause chips to fail while in service?
  12. What are the major levels of digital system abstraction and why are they used in testing? What are the potential advantages and disadvantages to working at a high level of abstraction when designing a test?
  13. What is the single fault assumption and why is it usually made in testing problems?
  14. Define the ``stuck-at fault'', ``bridging fault'', ``transistor fault'', ``gate delay fault'', ``path delay fault'', and ``crosspoint fault''.
  15. Define ``fault equivalence'' and ``fault dominance''. List all fault equivalences and fault dominances for both a 4-input NAND gate and a 3-input exclusive NOR gate.
  16. Given a simple combinational circuit, list the primary inputs, primary outputs, internal nodes, all possible stuck-at faults, equivalent stuck-at faults, and any dominance relationships among faults.
  17. In the context of boolean testing, what precisely is meant when a test is said to detect a fault?
  18. What is the difference between simulation and fault simulation?
  19. Is ``fault grading'' always necessary to determine ``fault coverage''?
  20. What is meant when a test pattern generation algorithm is said to be complete?
  21. Construct a high-level flowchart illustrating how test patterns are found using an unspecified, general test pattern generation algorithm.
  22. What is meant by the term ``backtracking''?
  23. Describe the five-valued algebra used in TPG algorithms?
  24. What is a ``sensitized path''?
  25. Explain how ``controllability'' and ``observability'' are both required to ensure ``testability''.
  26. What does the existence of circuits like `Sneider's example'' for test pattern generation algorithms?
  27. Define the processes of ``fault sensitization'', ``fault propagation'', and ``justification''.
  28. Give the primitive D-cubes and propagation D-cubes for the common logic gates (BUFF, INV, 3-input AND, 3-input NAND, 3-input OR, and 3-input NOR).
  29. Construct an execution trace for a version of the D-algorithm when presented with a simple combinational circuit that contains at least 6 logic gates. Identify the basic operations being performed at each step. Repeat assuming instead that PODEM is being used.
  30. What are the main differences between the D-algorithm and PODEM? Give some reasons why the running times for PODEM are generally faster than those for the D-algorithm, for most medium to large-sized circuits.
  31. Use static compaction to reduce the size of a small test set.
  32. Explain the difference between static and dynamic compaction.
  33. Describe the advantages and disadvantages of using random and deterministic test pattern generation algorithms. Why does random testing sometimes seem so efficient?
  34. What are the advantages and disadvantages of exhaustive testing?
  35. What is an (n,k)-exhaustive test?
  36. What makes sequential machines so difficult to test?
  37. What is the iterative array representation of a sequential circuit?
  38. Is it dangerous in practice to make the single fault assumption? Why or why not?
  39. What are the two faults known as ``CMOS faults''? How do they complicate the testing problem?