EE 651 - Digital System Testing and Design for Testability
Winter Session, Second Term
January - April, 2000
The final examination has been moved to CEB 231 because of a booking
conflict over V-114 with another class. The starting time will likely
be a little after 3pm to allow students to walk over from V-114 to the
new site. A sign will be posted at V-114 to redirect students back to
the new classroom.
The final examination was to have been held in the regular classroom (V-114)
on April 17. (The location has been changed to CEB 231.)
It will start at 3pm and will run for 120 minutes.
You will be permitted to consult your course notes, but not the
As discussed in our last class, there will be a review session today
at 3pm in the regular classroom (V-114). Please bring your questions
on all aspects of the course.
After returning the marked midterms, the first part of the class will
be a review of the solutions to the midterm questions.
Here is the long-awaited problem set 2.
The problems for assignment 2 are 2, 3, 6, 12, 13, 14, 15, 19 and 25,
all from problem set 2.
Your solutions are due at noon on Monday, April 17 in my mailbox
in CEB 238 or at my office in CAB 469. You should find that working
through these problems will help prepare you for the final exam, which
will be held in class on April 17 at 3pm.
The examination period will be two hours.
(The location has been changed to CEB 231 from V-114.)
A table containing downloadable slides from the oral presentations and
the assigned project topics is available below on
Here is the marking guide that was used before
to evaluate the oral presenations in the testing course.
A similar guide will be used again this year.
In addition, here is a list of tips for making oral
presentations that I prepared in a previous year.
Here is a list of project topics.
This is not a complete list; feel free to develop your own topic ideas.
You may wish to look through recent issues of journals and conference
proceedings to get additional project ideas.
Appropriate journals include IEEE Design & Test of Computers and
IEEE Transactions on Computers.
Good conference proceedings to check would be the
IEEE International Test Conference and the IEEE VLSI Test Symposium.
There are many more other smaller conferences, symposia, and workshops
that report research in the testing area.
List of additional practice problems from the course textbook:
3.2, 4.2, 4.3, 4.6, 4.11, 4.16, 6.12
The midterm for this course was originally supposed to be held in class
on February 14 (the week before Reading Week).
It will instead be held in class on Monday, February 28.
The examination period will be two hours.
You will be allowed to consult your copies of the course overheads.
Here is the long-awaited problem set 1.
For your first assignment please prepare solutions to problems 3, 5,
12, 15, 20, 25, 26, 29, 30, and 33. The assingment will be due on
Friday, February 18, by 4:00 in my mailbox in CEB 238.
Test CAD engineer job available in Ottawa at LogicVision.
The lecture room has been changed to V-wing, room V-114.
The day and time is the same as before, Mondays, 15:00 to 18:00.
The lecture time has been changed to Mondays, 15:00 to 18:00.
The new location is Chemistry room W 4-46, on the fourth floor.
Instructor: Dr. Bruce F. Cockburn,
office: CAB 469
Lecture Section: Lec B1 (course no. 21854)
The first lecture will be held at 12:30 on Tuesday, Jan. 11 in CAB 243.
Subsequent lectures will be held on a regular schedule, to be determined
at the first lecture, that is convenient to all class attendees.
The official calendar hours are Tuesday and Thurday running from 12:30
Many questions can be answered immediately before or after the class
Electronic mail should be used initially for most questions outside
of class times.
Appointments can be made by e-mail for longer in-person meetings.
Course Homepage URL: http://www.ee.ualberta.ca/~cockburn/ee651/
Consult the course homepage for the most up-to-date information on
course policies, deadlines, course handouts, project topic ideas,
presentation schedules, etc.
The lectures will be supplemented by hardcopy handouts, which will be
distributed in class over the course of the term.
An initial batch of notes will be distributed at the start of the
Student presentations are also expected to be supplemented with
handouts including, at least, hardcopies of the slides.
Digital Systems Testing and Testable Design, revised printing,
Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman,
IEEE Computer Sociey Press, Piscataway, NJ, ISBN 0-7803-1062-4.
I have purchased eight copies directly from the publisher, and will
make them available for sale at cost.
(U.S. $77.00 plus tax and shipping).
The Library will also have at least two copies available on reserve
under call number TK 7874 A112 1990.
Other Useful Reference Books:
Design for Test for Digital IC's and Embedded Core Systems,
Alfred L. Crouch,
Prentice-Hall PTR, Upper Saddle River, NJ, 1999, ISBN 0-13-084827-1.
Structured Logic Testing,
Edward B. Eichelberger, Eric Lindbloom, John A. Waicukauski,
and Thomas W. Williams, Prentice-Hall,
Englewood Cliffs, NJ, 1991, ISBN 0-13-853680-5.
In Cameron Library under call number TK 7868 L6 S927 1991.
Tutorial: VLSI Testing & Validation Techniques,
Hassan K. Reghbati, ed., IEEE Computer Society Press,
Piscataway, NJ, 1985, ISBN 0-8186-0668-1.
Delay Fault Testing for VLSI Circuits,
A. Kristic and K.-T. Cheng, Kluwer Academic Publishers, 1998.
The Test Access Port and Boundary-Scan Architecture,
Colin M. Maunder and Rodham E. Tulloss, eds.,
IEEE Computer Society Press, 1990, ISBN 0-8186-9070-4.
Bridging Faults and Iddq Testing,
Yashwant K. Malaiya and Rochit Rajsuman, eds.,
IEEE Computer Society Press, 1992, ISBN 0-8186-3215-1.
Testing Semiconductor Memories: Theory and Practice,
Ad van de Goor, John Wiley & Sons, 1991.
In Cameron Library under call number TK 7895 M4 G662 1991.
Random Testing of Digital Circuits,
Marcel Dekker Inc., 1998, ISBN 0-8247-0182-8.
Analog Signal Generation for Built-In Self-Test of
Mixed-Signal Integrated Circuits,
Gordon W. Roberts and Albert K. Lu,
Kluwer Academic Publishers, 1995, ISBN 0-7923-9564-6.
Calendar Course Description:
(second term, 3-0-0)
Designing and testing digital VLSI/ULSI systems.
Reliability issues of digital systems, testing algorithms,
Fault modelling, fault simulation, automatic test generation,
data compaction, and pseudorandom techniques, built-in self-test,
error detecting and correcting codes in digital system design
CAD tools for design testability.
Recommended prerequisites: EE 480 or EE 552 or equivalent.
Course Outline: (May vary slightly over the course of the term)
Introduction to Testing and Design for Testability
The Economics of Testing
Physical Defects and Fault Models
Combinational Logic Testing
Sequential Logic Testing
Mixed Analogue/Digital Circuit Testing
Structured Design for Testability
Built-In Self-Test and Self-Repair
Existing and Emerging Test Standards
||At least four during the term
||To be held in the classroom
||To be held in the last class
||Ask questions and get involved
|In-class Oral Presentation
||One research paper to be presented
||Due at the end of the exam period
Approximately five short homework assignments will be distributed during
Model solutions for all of the questions in each assignment will either
be distributed in class or made available on reserve in Cameron Library.
Date to be determined. Probably just before reading week, in class.
To be held during the last class meeting.
Grade Determination Method:
See section 23.4 in the 1998/99 University Calendar.
In this course, raw marks will be used up until after the final exam.
The resulting overall percentage mark will then be converted for each
student to a grade on the nine point scale.
A standard expected distribution of grades, which is provided by the Faculty
of Engineering, will be used as a rough guideline when mapping overall
marks to grades.
Code of Student Behaviour:
Refer to section 26 of the University Calendar for a comprehensive
discussion of what constitutes improper conduct for members of the
University community and for a description of disciplinary procedures.
In particular, note the definitions of plagiarism and cheating in
section 26.1.4 and the penalties for academic offences specified in
For example, cheating is defined as submitting the words, ideas,
images, or data of another person as the student's own in any academic
writing, essay, thesis, research project or assignment in a course or
program of study.
Penalties for academic offences range from a written reprimand up to
explusion from the University.
Hyperlinks to Related Resources on the WWW:
Course homepage for
304-649 VLSI Testing, offered at McGill University
Course homepage for ELEC 578: Integrated Circuit Design & Test, offered at UBC
Course homepage for ECE 255: VLSI Testing Techniques, offered at the University of California at Santa Barbara
Course homepage for EE 488: Testing Aspects of Computer Systems, offered at Stanford University
Course homepage for EE 658:
Diagnoisis and Design of Reliable Digital Systems, offered at the
University of Southern California
homepage for EE382M: VLSI Testing,
offered at the University of Texas at Austin
Course homepage for ECE
443: Digital System Testing and Design for Testability at the University of Illinois at Urbana-Champaign
Course homepage for ECE 55:138 Testing Digital Logic Circuits at the
University of Iowa at Iowa City.
IEEE Test Technology Technical Committee
CAD & Test Group,
University of California at Santa Barbara
Center for Reliable Computing, Stanford University
IGATE, University of Illinois at Urbana-Champaign
Soma's Mixed Analog Digital Test page, University of Washington
Mixed-Signal Test Bus Working Group home page
Standard for Embedded Core Test (SECT) Working Group home page
Oral Presentations and Course Project Topics:
||Presentation Topic & Date
||IC testers, March 20
||Multilevel DRAM characterization
||Faults in DRAM, March 20
||Multilevel DRAM characterization
||Error-correcting codes for RAMs, March 27
||Testing of embedded core based systems, March 20
|Yat King Chu
||Analog-to-digital converter testing, April 10
||Wrappers for IC core testing, April 3
||Core test methodology and scheduling
||Iddq testing, April 3
||IEEE P1149.4 mixed-signal test bus, April 10
||Using march tests to test SRAMs, March 27
||Oscillations & sequential behaviour in CMOS circuits, March 20
||CAM testing, April 10
||Transition fault simulation, April 3
||TPG for Sequential Circuits, April 10
||Interconnect testing for FPGAs, March 20
||Local Interconnect Testing for XC4000E FPGAa
||FIFO testing, April 3
||Detecting bridging faults with stuck-at fault test sets, March 27
||Testing for bridging faults
Last modified April 16, 2000 by B. Cockburn