ECE 512 - Digital System Testing and Design for Testability

Assignment #2

1. Logic simulators are classified as being either compiled-code (also called cycle-driven) or event-driven. Briefly describe these two simulator architectures. In each case, how does the simulation begin and how does it end? What are the major strengths and weaknesses of the two simulator architectures? What factors determine the relative efficiency of the two simulator architectures?

2. The major strategies for increasing the speed of fault simulation for combinational circuits (logic circuits without memory elements) attempt to exploit the inherent parallelism of the problem. For example, this problem involves simulating multiple independent test vectors for multiple very similar circuits (the good circuit and all of the possible faulty circuits). What would be the major challenges in designing a fault simulator for sequential circuits (logic circuits with memory elements)? Which parallelism strategies for combinational circuit fault simulation could be readily adapted for sequential circuits, and which strategies would not be appropriate?

3. Briefly describe the parallel and deductive fault simulation algorithms. Be sure to describe the major data structures that would need to be used to represent the signals in each of the two algorithms.

4. Heuristic testability measures are useful in several situations in digital circuit testing. Briefly describe how testability is computed for combinational networks involving NOT, NAND and NOR gates. What is the major weakness of heuristic testability measures?

5. In the context of automatic test pattern generation, briefly define what is meant by the following terms: (a) fault sensitization, (b) fault propagation, (c) line justification, (d) backtracking, and (e) backtracing?

6. Complete automatic test pattern generation algorithms have the useful ability to to find redundancies in logic circuits. What is meant here by the term "complete"? Redundancy can appear in a digital design either on purpose (as part of the intended design) or unintentionally. What would be two major reasons for deliberately adding redundancy to a digital circuit design? How could unwanted redundancy appear in a digital design?

7. Consider the logic circuit (called Example 7.3) that first appears in the class notes on slide 11-40. You are to construct two tables that illustrate what occurs when each of the D-Algorithm and the PODEM algorithm are used to find tests for the fault line "q" stuck-at-0. The table should have one column on the left to hold brief comments (e.g., fault sensitization, fault propagation, line justification, backtrack, etc.), columns for each of the three primary inputs (A, B, C), columns for the labelled internal lines (d, e, f, g, h, k, l, m, n, p, q, r, s, t, u, v), and columns for the three primary outputs (X, Y, Z). Note that not all of the internal lines appear in the list. The rows of the table are to indicate basic steps in each algorithm. The first row, with comment "Initial state", should have values of X for all signals. The X's should be replaced in the other rows with 0's, 1's, D's and D_bar's to illustrate the progress of the two algorithms. The last row should either end with a successful test vector, or the conclusion that no test vector exists for the fault.