Announcements:

• The midterm examination has been postponed for one week to Wednesday, November 8. There is not enough time to complete the model solutions and to finish the grading of your assignments before the original date of the exam.
• Assignment 2: Problems 5-17, 5-18, 5-26, 6-3, 6-5, 7-4, 7-6, 7-9, 8-6, 8-12 and 8-16 in the textbook. Due by the end of the class on Monday, October 30.
• Assignment 1: Problems 1-2, 2-2, 2-3, 3-5, 3-6, 3-7, 4-5, 4-11, 4-12, 5-10 and 5-16 in the textbook. Due by the end of office hours on Friday, October 13.
• The CCNET website for this course is available here.

Instructor: Dr. Bruce F. Cockburn, e-mail: cockburn@ece.ualberta.ca, office: ECERF W2-044

Lecture Section: Lec A1 (course no. 35097) The first lecture will be held from 9:00 to 9:50 on Wednesday, September 6 in ECERF W3-083. A MWF schedule will be followed thereafter in the same room.

Office Hours: Many questions can be answered immediately before or after the class meetings. Electronic mail should be used initially for most questions outside of class times. Appointments can be made by e-mail for longer in-person meetings.

Course Homepage URL: http://www.ece.ualberta.ca/~cockburn/ece512/fall2006/
Consult the course homepage for the most up-to-date information on course policies, deadlines, course handouts, project topic ideas, presentation schedules, etc.

Course Notes: The lectures will be drawn from a complete set of downloadable lecture notes prepared by the authors of the principal textbook. Additional readings may be distributed during the course of the term.

Principal Textbook: Essentials of Electronic Testing, M. L. Bushnell and V. D. Agrawal, Kluwer/Springer-Verlag, 2000, ISBN 0-7923-7991-8. Copies of the book should be available at the University bookstore.

Alternate Textbook: Digital Systems Testing and Testable Design, revised printing, Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman, IEEE Computer Sociey Press, Piscataway, NJ, ISBN 0-7803-1062-4. The Library has at least two copies available on reserve under call number TK 7874 A112 1990.

Other Useful Reference Books:

• Design for Test for Digital IC's and Embedded Core Systems, Alfred L. Crouch, Prentice-Hall PTR, Upper Saddle River, NJ, 1999, ISBN 0-13-084827-1.
• Structured Logic Testing, Edward B. Eichelberger, Eric Lindbloom, John A. Waicukauski, and Thomas W. Williams, Prentice-Hall, Englewood Cliffs, NJ, 1991, ISBN 0-13-853680-5. In Cameron Library under call number TK 7868 L6 S927 1991.
• Tutorial: VLSI Testing & Validation Techniques, Hassan K. Reghbati, ed., IEEE Computer Society Press, Piscataway, NJ, 1985, ISBN 0-8186-0668-1.
• Delay Fault Testing for VLSI Circuits, A. Kristic and K.-T. Cheng, Kluwer Academic Publishers, 1998.
• The Test Access Port and Boundary-Scan Architecture, Colin M. Maunder and Rodham E. Tulloss, eds., IEEE Computer Society Press, 1990, ISBN 0-8186-9070-4.
• Bridging Faults and Iddq Testing, Yashwant K. Malaiya and Rochit Rajsuman, eds., IEEE Computer Society Press, 1992, ISBN 0-8186-3215-1.
• Testing Semiconductor Memories: Theory and Practice, Ad van de Goor, John Wiley & Sons, 1991. In Cameron Library under call number TK 7895 M4 G662 1991.
• Random Testing of Digital Circuits, R. David, Marcel Dekker Inc., 1998, ISBN 0-8247-0182-8.
• Analog Signal Generation for Built-In Self-Test of Mixed-Signal Integrated Circuits, Gordon W. Roberts and Albert K. Lu, Kluwer Academic Publishers, 1995, ISBN 0-7923-9564-6.

Calendar Course Description: (second term, 3-0-0) Designing and testing digital VLSI/ULSI systems. Reliability issues of digital systems, testing algorithms, design-for-testability strategies. Fault modelling, fault simulation, automatic test generation, data compaction, and pseudorandom techniques, built-in self-test, error detecting and correcting codes in digital system design and testing. CAD tools for design testability.
Recommended prerequisites: EE/CMPE 480 or EE 552 or equivalent.

Course Outline: (May vary slightly over the course of the term)

From the official department course description

In previous offerings of the course the following outline has been used:

1. Introduction to Testing and Design for Testability
2. The Economics of Testing
3. Physical Defects and Fault Models
4. Combinational Logic Testing
5. Sequential Logic Testing
6. Fault Simulation
7. Memory Testing
8. Fault Diagnosis
9. Mixed Analogue/Digital Circuit Testing
10. Structured Design for Testability
11. Built-In Self-Test and Self-Repair
12. Existing and Emerging Test Standards

Evaluation Scheme:

Assignments: Approximately five short homework assignments will be distributed during the term. Model solutions for all of the questions in each assignment will either be distributed in class or made available on reserve in Cameron Library.

Midterm Examination: Date to be determined. Probably just before reading week, in class.

Final Examination: To be held during the last class meeting.

Grade Determination Method: See Section 23.4 in the University Calendar. In this course, raw marks will be used up until after the final exam. The resulting overall percentage mark will then be converted for each student to a grade on the nine point scale. A standard expected distribution of grades, which is provided by the Faculty of Engineering, will be used as a rough guideline when mapping overall marks to grades.

Code of Student Behaviour:

Refer to both Section 26 and Apendix A of the University Calendar for a comprehensive discussion of what constitutes improper conduct for members of the University community and for a description of disciplinary procedures. In particular, note the definitions of plagiarism and cheating in Section 30.3.2 in the Appendix and the penalties for academic offences specified in Section 30.4. For example, plagiarism is defined as submitting the words, ideas, images, or data of another person as the student's own in any academic writing, essay, thesis, research project or assignment in a course or program of study. Always cite the original sources of material that you wish to reference in your own work to make it clear that you are acknowledging the work of others, and that you are not claiming that work as your own. Penalties for academic offences range from a written reprimand up to explusion from the University.

Hyperlinks to Related Resources on the WWW:

• Course homepage for 304-649 VLSI Testing, offered at McGill University
• Course homepage for ELEC 578: Integrated Circuit Design & Test, offered at UBC
• Course homepage for ECE 255: VLSI Testing Techniques, offered at the University of California at Santa Barbara
• Course homepage for EE 488: Testing Aspects of Computer Systems, offered at Stanford University
• Course homepage for EE 658: Diagnoisis and Design of Reliable Digital Systems, offered at the University of Southern California
• Course homepage for EE382M: VLSI Testing, offered at the University of Texas at Austin
• Course homepage for ECE 443: Digital System Testing and Design for Testability at the University of Illinois at Urbana-Champaign
• Course homepage for ECE 55:138 Testing Digital Logic Circuits at the University of Iowa at Iowa City.
• IEEE Test Technology Technical Committee
• CAD & Test Group, University of California at Santa Barbara
• Center for Reliable Computing, Stanford University
• IGATE, University of Illinois at Urbana-Champaign
• Prof. Mani Soma's Mixed Analog Digital Test page, University of Washington
• IEEE P1149.4 Mixed-Signal Test Bus Working Group home page
• IEEE P1500 Standard for Embedded Core Test (SECT) Working Group home page

Last modified September 5, 2006 by B. Cockburn