[20 marks]
The ETPU_TBCR contains a variety of bit fields. The TCR1 signal is configured
by the TCR1CTL field (bits #15-14) and the TCR1P field (bits #7-0). In addition,
if TCR1 is derived from the external clock signal at pin TCRCLK, then the
TCRCF field (bits #28-27) are relevant to defining TCR1. After a reset the
clock source for the TCR1 prescaler is the external signal TCRCLK.
The TCR1CTL field can be written with two defined values: Value 00 causes TCRCLK to be used as the clock source for the TCR1 prescaler. Value 10 causes the internal bus clock, divided by two, to be used as the clock source for the TCR1 prescaler.
The TCR1P field, incremented by 1, defines the divide factor that is used in the TCR1 prescaler to produce the TCR1 clock from the filtered clock. The value of the divide factor can vary from 1 (TCR1P = 0) to 256 (TCR1P = 255).
The TCRCF field has two bits that determine the source of the filtered clock and the filter mode used to process that filter clock. If bit #27 is 0 then the source of the filtered clock is the system clock divided by 2; otherwise, if the bit is 1 then the source of the filtered clock is the same as the clock source used to filter the channel inputs to the eTPU. If bit #28 is a 0 then the filter clock is filtered using "two sample" mode (i.e., TCRCLK pulses that are two filter clock periods wide or less are filtered away); otherwise, the filter clock is filtered using "integration mode".
[12 marks]
All three classes of busses share the major characteristics of microcomputer
busses, including the presence of a data lines, address lines, and control lines
(including clock or other synchronization signals).
Processor-memory busses are optimized for the highest possible performance (within cost constraints) since they are a major bottleneck in system performance. These busses are optimized for the signals of the particular processor and the memory modules that it will be accessing (e.g. cache SRAM or synchronous DRAM).
Input/output, peripheral, and instrument busses are optimized for flexibility to allow the widest possible variety of devices, with a wide range of response times, to be connected together in a simple and convenient way. To achieve this flexibility in timing, some busses (e.g. the GPIB) use asynchronous timing, in which a clock signal is replaced by handshake signals. Other busses gain the flexibility by using semisynchronous timing schemes.
A backplane bus is intended to provide a bus that allows microcomputer systems to be rapidly assembled from a family of compatible boards. Such a bus provides a balance between performance (reasonably high-speed operation) and cost-effectiveness (so that the resulting bus-compatible boards will not be overly expensive). There will generally be a less stringent requirement for timing flexibility since the bus will be intended for boards that are all manufactured using similar technologies. However, there may be the need to provide compatibility with older "legacy" busses so that the new bus can take advantage of the available older boards.
[8 marks]
A split bus transaction is a bus transaction that is split up into two subtransactions
so as to free up the bus for other transactions. For example, a split read transaction
is split up into a first bus transaction that communicates a request for a certain block
of data starting at a certain address within the target device, and a second bus transaction
in which the target device communicates back the data that was requested. If the target device
is a relatively slow memory, splitting up the transaction in this way allows the system bus
to be used for other bus transactions during the slow access interval.
[20 marks]
The TS output from the MCF5234 is pulsed low (active) for one
CLKOUT cycle to indicate the start of a bus transaction.
The TIP output from the MCF5234 is pulsed low (active) and held low for a whole number of CLKOUT cycles as the bus transaction is taking place. The TIP is held continuously low (active) as long as adjacent bus transactions are occurring.
The TA input to the MCF5234 is pulsed low (active) by external circuitry when the external device has finished its part of the transfer, and is ready to end the transaction. The TA must go active at least one set-up time before a rising transition of CLKOUT, and must be held active for the hold time after that same clock transition. The TA input is used only when the transaction involves addresses that are outside of the MCF5234.
The TEA input to the MCF5234 is pulsed low (active) by external circuitry to warn the CPU that an error has occurred during the transfer. This will then cause the CPU to begin executing the access error exception handling routine. the TEA input must also respect set-up and hold time constraints with respect to a rising transition of CLKOUT. The TA input is used only when the transaction involves addresses that are outside of the MCF5234.
[15 marks]
The mode is selected by the Cycle Steal (CS) bit (bit #29) in the DMA Channel
Control Register (DCRn). Bit value 0 selects continuous mode and bit value 1
selects cycle steal mode.
Cycle steal mode allows an external device to select one DMA transfer to occur, interleaved with other bus transfers on the external system bus. If the DMA Request (DREQn) line is held active (low) for less than the transfer time, then only a signal data block will be transferred. If DREQn is held low longer than this time, then a burst of DMA transfers will be caused for as long as DREQn is held low. A cycle stealing DMA transfer can also be initiated by the CPU by writing a 1 to the START bit (bit #16 in the DCRn).
Continuous mode will, depending on the value loaded in the Bandwidth Control (BWC) field (bits #27-25) of the DCRn, cause a burst of data transfers to occur on the external bus once DMA has started. BWC value 0b000 causes all of the data transfer to occur in one block. BWC values of 0b001 up to 0b111 cause increasingly large blocks (up to 1025 bytes) to be transfered before the DMA burst ends to allow the external bus to be used for another purpose. Continous A continuous DMA burst can also be ended by the CPU by writing a 1 to the DONE bit (bit #0) in the DMA Status Register (DSRn).
One must consider system-level factors to properly select the DMA transfer mode. If there are multiple DMA transfers occurring with roughly equal importance and priority, then the cycle stealing mode should probably be used. If there is one DMA transfer that is much more important than other activities, then the DMA transfer should probably be done in continuous mode. In continuous mode the BWC field could be used to break up the length of the bursts to ensure that other system activities are not overly delayed.
[10 marks]
The GPIB is an asynchronous and multilateral bus that provides a wide degree
of flexibility to allow controllers and other devices (with talker and/or
listener capability) of very different response times to work together
over a relatively simple 16-wire bus cable. Instruments tend to be used
for a long time, and as they become older, they need to be interfaced with
much faster, more modern equipment.
The GPIB is designed to accommodate the slowest possible device that participates in each bus transaction. There is no clock signal since a fixed clock signal would provide an inflexible timing speed. Instead, three active-low handshake signals are used: data valid (DAV), not ready for data (NRFD), and not data accepted (NDAC). These signals are driven by open collector drivers, so that they actually perform a "wired-AND" operation (a resistor connected to the positive supply voltage will pull the wire voltage high only if none of the connected drivers is actively driving the wire voltage low). The NRFD line will go high only when all devices are ready for the data transfer, and the NDAC line will go high only when all devices have completed the the data transfer. The DAV signal is driven low whenever the data on the eight data bus lines has stable and valid values.
A data transfer over the GPIB proceeds as follows: The DAV line is high (inactive) at the end of the previous data transfer; also, the NDAC line is low. The device that is to drive new data values starts to drive them onto the 8-wire data bus. Meanwhile, the various GPIB devices that were involved in the data transfer will turn off their NRFD drivers; when the slowest device is ready for the next data transfer, the NRFD line will high. Once NRFD is high and the data bus signals are stable, the DAV line is driven low (active) to signal that fact to the other devices on the bus. At their own pace, each device that needs to load the data from the bus will latch in the data, and then stop driving the NDAC line low. When the slowest device has latched in the data, then the NDAC line will go high (inactive). When that happens, the originator of the new data can safely drive the DAV line high (inactive) and start to change the values on the data bus. When the DAV line goes high, the other devices on the bus stop driving the NRFD line low; the DAV line will not be driven low again before the NFRD line goes high again, indicating that all devices are again ready to receive new data.
[15 marks]
The active-low signals IRDY and TRDY are used to signal when the initiator
and the target devices, respectively, are ready for a data tranfer over the
PCI bus. The data transfer (read or write) occurs at the next rising edge
of the PCI clock signal. Both IRDY and TRDY must be low for the data
transfer to proceed. This allows both the initiator and target devices to
delay the data transfer by some sufficient number of whole PCI clock cycles.
For example, during a read operation over the bus, the CPU might assert the
IRDY line low right away, but a slower memory device might hold back asserting
the TRDY line low until it had fetched the data from its internal data storage
elements.