CMPE 401 - Computer Interfacing

Assignment #2

1. Design an assembly language subroutine that scans through a packed array of longwords and computes the following two numbers: (1) the number of 1's present in all bytes at odd-numbered byte addresses, and (2) the number of 0's present in all bytes at even-numbered byte addresses. The subroutine is to be called BIT_COUNT. The 32-bit addresses of the first and last longwords in the array are to be pushed onto the stack immediately before BIT_COUNT is called. The number of 1's and the number of 0's are to be returned in D1.W and D0.W, respectively. No other CPU register bits are to be altered by the time that execution has returned from BIT_COUNT to the calling routine.

2. Slide 3-11 in the course notes illustrates the scheduling behaviour of a simple multitasking system with two tasks, Task A and Task B, that are scheduled to execute regularly at two different frequencies. Task B is scheduled to execute its software states at exactly twice the rate of Task A. In your own words describe a design, using the MicroC/OS pre-emptive multitasking environment, that implements the behaviour in Slide 3-11. Assume that Task B is scheduled to run every 20 milliseconds. Further assume that the hardware timer produces 200 ticks per second. Use C code to describe your task designs. However, you do not have to produce a compileable MicroC/OS system, with full initialization code. Hint: It might be useful to introduce a new task and two semaphores.

3. Briefly define what is meant by a "noise margin" in the case of digital logic. What is the main purpose of having nonzero noise margins at a digital interface.

4. Consult Chapter 26 in the MCF5235 Reference Manual (MCF5235.pdf) and then briefly explain the events that are associated with bits #7, 2, 1 and 0 of the UART Interrupt Status and Mask Registers (UISR and UIMR).

5. Briefly explain the general functionality provided by an Ethernet PHY chip, such as the the Micrel KS8721BT. Why has it been important for the industry to standardize the interface between the PHY and the MAC device?

6. Consult Chapter 19 in the MCF5235 Reference Manual (MCF5235.pdf) and then briefly explain how software running on the ColdFire CPU can write and read values to the registers in the PHY over the MII/MDIO interface using the MII Management Frame Register (MMFR). Note: A "MII Management Frame" is a 32-bit long formatted data packet that is shifted serially onto the MDIO line by the rising edges of the MDC clock signal. Usually, the MAC drives the MDIO line and the PHY latches the arriving bits into the specified internal PHY register. In the case of MII Management Frames that request a PHY register read, however, the data direction on the MDIO line is reversed for the last 16 bit times in the frame, when the PHY drives the 16 bits that are shifted out from the one addressed internal PHY register. The detailed operation of the MDIO and MDC lines is controlled automatically by the FEC/MAC block, with no intervention by the CPU. How can the CPU be notified, using an FEC interrupt, that the current MII Management Frame has been successfully transmitted to the desired PHY?

7. Briefly describe how the W and L bits are used in the FEC transmit buffer descriptors. Also explain how the transmit buffer descriptors are used together in the transmit buffer descriptor ring.