CMPE 401 - Computer Interfacing

Assignment #4

Model Solutions

 

  1. In the lectures we reviewed the definitions of set-up time and hold time. These parameters are important in all synchronous digital systems, and not just in computer busses. In your own words explain the physical source of these two time constraints. If one were to discover that a set-up time constraint was violated in a general digital system, causing system malfunction, what could be done to fix the problem (assuming that one could modify the design at the gate and internal wiring level)? What could be done to fix violations of hold time constraints?

 

Setup time, tsu is the minimum length of time a signal must be valid at a first input before a triggering signal arrives at a second input (e.g. a clock signal).  This is required to overcome the effect of the internal capacitances (which must be charged and discharged) and must be obeyed to ensure that the flip-flop stabilizes correctly after an edge-triggered sample signal arrives.  Setup time violations may be overcome by slowing down the system clock.  Reducing the internal capacitances would also work.

 

Hold time, tho is the minimum length of time a signal must be valid at an input after a triggering signal arrives at a second input.  This constraint is required to allow the triggering signal to propagate through the flip-flop circuitry and ensures that the input signal is sampled correctly.  Hold time violations may be overcome by delaying changes in the input data signal (with a buffer), or by speeding up the operation of the flip-flop (if possible).

 

  1. In addition to read bus cycles and write bus cycles, the 68000 also provides a combined read-modify-write bus cycle. Consulting the on-line documentation if necessary, briefly explain why this third kind of bus cycle is required to implement the test and set (TAS) instruction.

 

The test and set instruction tests a byte, updates the N and Z flags of the CCR accordingly (and clearing V and C), and sets bit 7 of the byte.  It is primarily used in multiprocessor systems to indicate that regions of memory are in use by another processor (when the N bit is set after TAS) or available for use (when N is clear).  While TAS could be implemented with a read cycle followed by a write in a single processor system, a read-modify-write is necessary for the processor executing the TAS instruction to retain control of the bus in between the read and the write.  The RMC signal is asserted to indicate (to a bus master) that a read-modify-write operation is underway and should not be interrupted.


  1. Briefly explain how the bus size signals (SIZ0 and SIZ1) are used along with the data size acknowledge signals (DSACK0 and DSACK1) to permit the orderly transfer of bytes, words and longwords between the CPU and peripheral devices of variable data bus port width.

 

The CPU indicates the remaining number of bytes to be transferred to a peripheral device on the data bus using SIZ1 and SIZ0. SIZ1,0 used together indicates 4 bytes remaining (00), 3 bytes (11), 2 bytes (10), or 1 byte (01).  Peripheral devices use together to indicate the width of its data bus, either a byte (10) or a word (0X).  During a data transfer, it can also be used to slow down the transfer by requesting that the CPU insert wait cycles (by using, and holding, 11).  As an example, the transfer of a long word on a byte-sized bus involves using 4 transfer cycles, with the CPU decrementing the number of bytes remaining by 1 after each transfer (and signaling this using SIZ1,0).

 

  1. From the 68000 timing diagrams that appeared in the lecture slides determine the following time intervals:
    • In a write cycle, what is the maximum possible delay from the 80% point on the first rising edge of the first clock pulse, to the time when the address line function code signals are valid (that is, have reached 20% of their final values, either high or low)?
    • In a write cycle, what is the minimum delay between when the data bus signals are valid, and the time when the data strobe signal goes valid low? This second time is the moment when the data is written into the interface of the addressed destination.
    • In a read cycle, what is the minimum hold time from the time when the data strobe (DS) signal goes inactive (high), and the time when the data on the data bus is no longer valid?

Assuming a 16.78 MHz clock, the following values are given for the above parameters from the read/write timing diagram legend:

·        Maximum value of tCHAV (clock high to function code valid) is 29 ns

·        Minimum value of tDVSA (data out valid to data strobe asserted) is 15 ns

·        Minimum value of tSNDOI (data strobe negated to data out invalid) is 15 ns

 

 

 


  1. The 68000 bus arbitration control interface provides three signals: input bus request (BR), output bus grant (BG), and input bus grant acknowledge (BGACK). The interface also involves the data acknowledge (DTACK) and address strobe (AS) signals. The basic interface allows a 68000 to be simply connected to one alternate bus master, but a special arbiter is required to handle two or more alternate bus masters. Propose an arbiter unit design that could allow three 68000s to share the same bus. Be sure to specify the signals that would need to be connected to the arbiter, and design an algorithm based on rotating priorities that would ensure fair sharing of the bus. Your design solution just has to specify a correct behaviour; it is not necessary to come up with a complete gate-level design.

 

Each of the three 68000s must have their BR, BG, and BGACK lines connected separately to the bus arbiter, with the other bus signals connected to a common bus.  An example of a simple arbitrating algorithm allows a 68000, once it wins control of the bus, to have exclusive control until it surrenders control (burst mode).  The devices initially begin with a certain priority order that rotates after each bus use (e.g. from highest to lowest priority 123, followed by 231, then 312, and back to 123).  When the bus is not in use, any of the processors may take control of the bus when requested.  When the bus is in use, a processor requesting control of the bus is queued according to its priority.  Once the processor currently in control of the bus relinquishes control, the priorities are rotated and the next processor in the queue is allowed to take control of the bus.

 

The arbiter asserts the bus grant acknowledge BGACK to each of the 68000s.  A device requests bus control by asserting the bus request BR, which is either granted by the arbiter (via asserting of bus grant BG and negating of BGACK) or the request may be queued.  When a device has its BG signal asserted by the arbiter (and BGACK is negated) it asserts BGACK and negates BR.  The arbiter responds by negating the BG signal going to the processor and waits for it to finish using the bus (signaled by the processor negating BGACK).  The arbiter then allows the next queued device to take control (in the same way as above) or waits for another device to request use of the bus.