CMPE 401 - Computer Interfacing

Assignment #4

1. In the lectures we reviewed the definitions of set-up time and hold time. These parameters are important in all synchronous digital systems, and not just in computer busses. In your own words explain the physical source of these two time contraints. If one were to discover that a set-up time contraint was violated in a general digital system, causing system malfunction, what could be done to fix the problem (assuming that one could modify the design at the gate and internal wiring level)? What could be done to fix violations of hold time constraints?

2. In addition to read bus cycles and write bus cycles, the 68000 also provides a combined read-modify-write bus cycle. Consulting the on-line documentation if necesary, briefly explain why this third kind of bus cycle is required to implement the test and set (TAS) instruction.

3. Briefly explain how the bus size signals (SIZ0 and SIZ1) are used along with the data size acknowledge signals (DSACK0 and DSACK1) to permit the orderly transfer of bytes, words and longwords between the CPU and peripheral devices of variable data bus port width.

4. From the 68000 timing diagrams that appeared in the lecture slides determing the following time intervals:
   • In a write cycle, what is the maximum possible delay from the 80% point on the first rising edge of the first clock pulse, to the time when the address lins function code signals are valid (that is, have reached 20% of their final values, either high or low)?
   • In a write cycle, what is the minimum delay between when the data bus signals are valid, and the time when the data strobe signal goes valid low? This second time is the moment when the data is written into the interface of the addressed destination.
   • In a read cycle, what is the minimum hold time from the time when the data strobe (DS) signal goes inactive (high), and the time when the data on the data bus is no longer valid?

5. The 68000 bus arbitration control interface provides three signals: input bus request (BR), output bus grant (BG), and input bus grant acknowledge (BGACK). The interface also involves the data acknowledge (DTACK) and address strobe (AS) signals. The basic interface allows a 68000 to be simply connected to one alternate bus master, but a special arbitor is required to handle two or more alternate bus masters. Propose an arbitor unit design that could allow three 68000s to share the same bus. Be sure to specify the signals that would need to be connected to the arbitor, and design an algorithm based on rotating priorities that would ensure fair sharing of the bus. Your design solution just has to specify a correct behaviour; it is not necessary to come up with a complete gate-level design.