CMPE 401 - Computer Interfacing

Assignment #3

1. Briefly describe how the TCP segments travelling in the two opposite directions of a TCP connection interact. In your answer, explain what events can be triggered in the transmit direction when a new segment arrives at an end node in the receive direction.

2. An autovectored 68000-class microcomputer has seven different interrupt priority levels (IPLs). What would be a reasonable mapping of external interrupts to these seven IPLs given the following external interrupt sources? (a) mouse movement and/or button pressed; (b) game console button(s) pressed; (c) new data packet received by the network interface card (NIC); (d) transmit data buffer empty in the NIC; (e) transmitted packet acknowledgement time-out in the NIC; (f) supply voltage monitor (e.g. power failure detected); (g) general-purpose hardware timer #1 (used for time slicing); (h) general-purpose hardware timer #2 (used for producing real-time control signals); and (i) general-purpose hardware timer #3 (available for other applications). Note that there are more than seven interrupt sources, so the interrupt service routines for some IPLs will be shared for multiple interrupt sources. Carefully justify your ranking of these interrupts. State your reasonable assumptions about system operation.

3. What makes Direct Memory Access (DMA) such a fast method for transferring blocks of data between two regions in memory? What factors make DMA less efficient for transferring small blocks of data (compared to, say, using multiple microprocessor MOVE instructions).

4. Briefly explain what is meant by virtual memory. (If necessary, consult a reference on basic computer architecture, or consult an Internet tutorial article.) Then explain why at page boundaries, memory locations with adjacent physical addresses do not necessarily have adjacent virtual addresses. Why does this fact complicate the implementation of DMA in computer systems with virtual memory?

5. Briefly describe the operation of a ping-pong buffer. What would be a reasonable algorithm for determining when the two buffers should swap roles? Give pseudo-code that specifies your algorithm. What are the main constraints that must be respected in any such buffer control algorithm?

6. Consult the on-line documentation for the TPU (available by following the link from the course homepage) to determine how the "Pulse Width Modulation" built-in function works (function code $9). Briefly explain, in your own words, the capabilities of this function. Your explanation should describe what is meant by terms "pulse width modulation" and "duty cycle".