CMPE 401 - Computer Interfacing

Assignment #5 Model Solutions

1. The TPU Interrupt Service Routine (ISR) for a MicroC/OS-II environment shown below contains multiple programming errors. The ISR is to be used to unblock (i.e. signal) a task, which is waiting on a semaphore, when the TPU Stepper Motor function has finished the last host service request. Indicate, by directly writing on the code, where all of the errors are. Also indicate how the errors could be most easily corrected. State any important assumptions that you are making in your proposed corrections to the code:

   
   TPU_ISR:   ADDQ.B   #1,OSIntNesting
              MOVEM.L  A0-A7/D0-D7,-(SP)
              LEA.L    #TPU_BASE_ADDR,A0
              MOVE.B   TPU_CISR(A0),D0
              ANDI.W   #SM_PRIM_IRQBIT,D0
              BNE      EXIT_TPU_ISR
              MOVEM.L  A0-A7/D0-D6,-(SP)
              PEA.L    TPU_Semaphore
              JSR      OSSemPend
              MOVEM.W  (SP)+,A0-A7/D0-D7
              ADDQ.L   #2,SP
   EXIT_ISR:  JSR      OSIntExit68K
              MOVEM.L  (SP)+,A0-A7/D0-D7
              RTS
   
   

   [15 marks]
   Corrections are shown below in bold font.

   
   TPU_ISR:   ADDQ.B   #1,OSIntNesting
              MOVEM.L  A0-A6/D0-D7,-(SP)
              LEA.L    TPU_BASE_ADDR,A0
              MOVE.W   TPU_CISR(A0),D0
              ANDI.W   #SM_PRIM_IRQBIT,D0
              BEQ      EXIT_TPU_ISR
              MOVEM.L  A0-A6/D0-D7,-(SP)
              PEA.L    TPU_Semaphore
              JSR      OSSemPost
              ADDQ.L   #4,SP
              MOVEM.W  (SP)+,A0-A6/D0-D7
              /* ADDQ.L   #2,SP  delete this line */
              /* must now clear the IRQ bit */
              MOVE.W   #SM_PRIM_IRQBIT,D1
              NOT.W    D1
              AND.W    D1,TPU_CISR(A0)
   EXIT_TPU_ISR:  
              JMP      OSIntExit68K
              /* MOVEM.L  (SP)+,A0-A7/D0-D7  delete this line */
              /* RTS   delete this line */
   
   

2. Backplane busses, such as VME or PCI, are useful for reducing the design cost and to reduce the "time-to-market". Third-party circuit boards for these busses are typically loaded down with many features to make them attractive to as many potential customers as possible. What do you think would be potential disadvantages to selling a system constructed using third-party boards if the production volume of your system is likely to be large?

   [10 marks]
   Third-party boards are designed to appeal to as many potential customers as possible, and so they tend to be loaded down with many features. Such a board will thus likely be more expensive to manufacture than a board that is optimized for the actual end application. An optimized board will only have the required hardware elements, and no more. Also, a board that is manufactured by a third party will be priced to include profit for that third party manufacturer, implying that there will be less profit available for you own company (assuming that you are building systems to sell at a profit).

   Thus the major disadvantage of third-party boards is that they will be more expensive that they could be if you could use boards that are optimized for the desired application. For small production runs, when the time-to-market is critical, it may be more economical to use third-party boards. However, as the production volumes become larger, a point is reached where it is more economical to build and manufacture customized boards.

3. Synchronous memory elements require that minimum set-up time and minimum hold time constraints between the data input signals and the clock signal be respected; otherwise, the memory element may not work properly. What is the underlying physical reason for the set-up and hold time constraints? (Hint: What needs to happen to change the voltage on a conductor?)

   [15 marks]
   In order to change the state of a flip-flop in a predictable manner, the inputs must be held steady for some finite period of time in both the old state (before the active clock edge) and the new state (after the active clock edge). In the old state, the inputs must have been held steady long enough to allow all of the electrical nodes within the flip-flop to reach stable values. This minimum time is ensured by the set-up time constraint. The process of reaching a stable state takes a finite amount of time because it takes a finite amount of time to change the voltage of electical conductors by moving electrical charge to and from the finite capacitance of those conductors. Right after the clock changes to the new value, the internal state of the flip-flop will take a finite amount of time to stabilize in response to the new clock value. This minimum time is ensured by the hold time constraint.

   It is much easier to design flip-flops when it can be assumed that sufficiently long set-up and hold times are respected before and after the clock edge, respectively. Flip-flops typically appear in large numbers in digital system designs, and so it is desirable to keep them as simple, and as small, as possible. The set-up and hold time constaints thus help ensure that the flip-flop design will be simpler.

4. The original MC68000 did not have an A0 address line. Instead an Upper Data Strobe (UDS) and a Lower Data Strobe (LDS) were provided. Why do you think that it would attractive to provide the A0 information in this way using UDS and LDS? If Motorola had provided A0 instead of UDS and LDS, what other signals would be required to allow the MC68000 to access 8-bit as well as 16-bit peripheral devices?

   [15 marks]
   There are three possibilities if the MC68000 is to access both 8-bit and 16-bit devices over a 16-bit-wide databus. Recall that 16-bit devices must be aligned on even-numbered addresses whereas 8-bit devices can be aligned on either odd or even-numbered addresses. Therefore the CPU needs to output at least two different signals to encode the three different possibilities.

   The advantage of the UDS and LDS signals is that they can be used in the same way without the need for any further combinational logic. UDS can be used alone to enable even-aligned 8-bit devices, and LDS can be used alone to enable odd-aligned 8-bit devices. For even-aligned 16-bit devices, either one of UDS and LDS can be used to enable the device. Thus the main attraction of the UDS and LDS signals is that all three device interfacing possibilities can be handled without the need for any further logic gates. Also, each peripheral device requires only one enable input.

   If A0 were to be retained, then at least one additional signal would be required to distinguish between even-aligned 8-bit devices and even-aligned 16-bit devices. Thus the number of external signals would still be two, compared with the use of UDS and LDS. And using A0 along with a second signal would either require additional decoding logic (to produce a signal peripheral enable signal), or an additional peripheral device input for receiving the second signal (with the two input signal being decoded inside the peripheral).

   In the 68332, the problem is solved by including an A0 address line, and also requiring that 8-bit devices be aligned on even addresses. When an 8-bit device is addressed, the lower 8 bits on the data bus are don't care signals that are ignored.

5. Briefly explain the behaviour and potential uses of the three function code bits, FC0-FC2, in the 683xxx system bus. In your answer, explain how the FC bits might facilitate system debugging and system security.

   [15 marks]
   The three function code signals are updated with the same timing as the address outputs from the 68332. They can be thought of as address extensions. It is possible to decode the FC bits to produce eight distinct address spaces. (However, not all 8 combinations are used. Three combinations are reserved for future uses.) More specifically, the FC bits are used to indicate the type of bus operation that is occuring, as shown in the following table:

   FC2	FC1	FC0	Operation Type
   0	0	0	Reserved
   0	0	1	User data space (i.e. R or W of user data)
   0	1	0	User program space (i.e. R of user program)
   0	1	1	Reserved
   1	0	0	Reserved
   1	0	1	Supervisor data space (i.e. R or W of supervisor data)
   1	1	0	Supervisor program space (i.e. R of supervisor program)
   1	1	1	CPU space (i.e. IACK cycle, etc.)

   The "CPU space" includes special bus operations, including the "Interrupt Acknowledge Cycle".

   The FC bits can be used to facilitate debugging, and to increase system security, because these signals can be monitored by a hardware circuit that prevents (and/or logs) attempts by user programs to alter program data (user or supervisor) or supervisor data. In addition, attempts by supervisor programs to alter supervisor programs, or user programs or data, can be flagged, logged, or entirely prevented in hardware.

6. Briefly explain how the two data size signals, SIZ0 and SIZ1, are used by the CPU together with the two data size acknowledge signals, DSACK0 and DSACK1, to allow the 683xxx bus to automatically resize itself during the transfer of bytes, words and long-words.

   [15 marks]
   The data size signals, SIZ1 and SIZ0, are used to indicate the number of bytes that remain to be transferred duing a bus operation, as follows:

   SIZ1	SIZ0	Transfer size
   0	1	Byte
   1	0	Word (2 bytes)
   1	1	Three bytes
   0	0	Long word (4 bytes)

   The data size acknowledge signals, DSACK1 and DSACK0, are used by a memory-mapped device (e.g. memory or peripheral) to (1) indicate to the CPU the size of the data port of the device that the CPU is addressing, and (2) to provide a timing handshake signal from the peripheral to indicate to the CPU that the read/write operation has completed successfully at the peripheral. Both DSACK1 and DSACK0 are active low signals: specifically, they go low in voltage near the start of the bus operation, and then later rise in voltage near the end of the bus operation. The following table indicates the meaning of DSACK1 and DSACK0:

   DSACK1	DSACK0	Meaning
   1(L)	1(L)	Insert wait states; peripheral not finished
   1(L)	0(H)	8-bit peripheral has finished reading/writing
   0(H)	1(L)	16-bit peripheral has finished reading/writing
   0(H)	0(H)	Reserved (normally the idle state)

7. What is the difference between cycle stealing mode and burst mode Direct Memory Access (DMA)? How does the peripheral controller request each kind of mode when it wishes to transfer data over the system bus?

   [15 marks]
   In cycle stealing DMA, the DMA-controlled bus cycles are interleaved, on demand, with regular CPU-controller bus cycles. Each DMA bus cycle is requested separately. In burst mode DMA, the DMA-controlled bus cycles are occur in bursts of consecutive DMA cycles. Once a sequence of DMA cycles has started, the DMA controller can continue to generate more DMA cycles for as long as it needs.

   The different kinds of DMA are coordinated among the peripheral controller, DMA controller and CPU using special signals. In the case of the M68340 DMA controllers, the external peripheral controller interacts with the DMA controller (one of the two such controllers inside the 68340) by means of the following three signals:

   1. DREQ (DMA request) is an active low signal that is used by the peripheral controller to request a DMA transfer. The corresponding DMA transfer will occur later in a future bus cycle.
   2. DACK (DMA acknowledge) is an active low signal that is used by the DMA controller to indicate that the next DMA transfer is about to begin in the present bus cycle.
   3. DONE (DMA done) is a bidirectional active low signal. It can be driven by the DMA controler to indicate that the DMA transfer in the present bus cycle will be the last DMA transfer.

   To produce DMA cycle stealing, the peripheral controller requests one DMA cycle by pulsing DREQ low (active). The DMA transfer will then occur in a future bus cycle when DMACK next goes low (active). To produce DMA using burst mode, the peripheral controller asserts DREQ low (active) and holds it low for as long as it wants. When the DMA controller acquires control of the system bus, it asserts DACK low (active) and a sequence of DMA cycles begins. This sequence will continue until one of two events occurs: (1) The peripheral controller asserts DONE low (active) during one DMA cycle. There will be one more DMA cycle, but it will be the last one. (2) The DMA controller asserts DONE low (active) when during the last DMA cycle. This would occur when the DMA byte transfer counter inside the DMA controller indicates that the current DMA transfer is the last DMA transfer.