CMPE 401 - Computer Interfacing

Assignment #5

1. The TPU Interrupt Service Routine (ISR) for a MicroC/OS-II environment shown below contains multiple programming errors. The ISR is to be used to unblock (i.e. signal) a task, which is waiting on a semaphore, when the TPU Stepper Motor function has finished the last host service request. Indicate, by directly writing on the code, where all of the errors are. Also indicate how the errors could be most easily corrected. State any important assumptions that you are making in your proposed corrections to the code:

   
   TPU_ISR:   ADDQ.B   #1,OSIntNesting
              MOVEM.L  A0-A7/D0-D7,-(SP)
              LEA.L    #TPU_BASE_ADDR,A0
              MOVE.B   TPU_CISR(A0),D0
              ANDI.W   #SM_PRIM_IRQBIT,D0
              BNE      EXIT_TPU_ISR
              MOVEM.L  A0-A7/D0-D6,-(SP)
              PEA.L    TPU_Semaphore
              JSR      OSSemPend
              MOVEM.W  (SP)+,A0-A7/D0-D7
              ADDQ.L   #2,SP
   EXIT_ISR:  JSR      OSIntExit68K
              MOVEM.L  (SP)+,A0-A7/D0-D7
              RTS
   
   

2. Backplane busses, such as VME or PCI, are useful for reducing the design cost and to reduce the "time-to-market". Third-party circuit boards for these busses are typically loaded down with many features to make them attractive to as many potential customers as possible. What do you think would be potential disadvantages to selling a system constructed using third-party boards if the production volume of your system is likely to be large?

3. Synchronous memory elements require that minimum set-up time and minimum hold time constraints between the data input signals and the clock signal be respected; otherwise, the memory element may not work properly. What is the underlying physical reason for the set-up and hold time constraints? (Hint: What needs to happen to change the voltage on a conductor?)

4. The original MC68000 did not have an A0 address line. Instead an Upper Data Strobe (UDS) and a Lower Data Strobe (LDS) were provided. Why do you think that it would attractive to provide the A0 information in this way using UDS and LDS? If Motorola had provided A0 instead of UDS and LDS, what other signals would be required to allow the MC68000 to access 8-bit as well as 16-bit peripheral devices?

5. Briefly explain the behaviour and potential uses of the three function code bits, FC0-FC2, in the 683xxx system bus. In your answer, explain how the FC bits might facilitate system debugging and system security.

6. Briefly explain how the two data size signals, SIZ0 and SIZ1, are used together with the two data size acknowledge signals, DSACK0 and DSACK1, to allow the 683xxx bus to automatically resize itself during the transfer of bytes, words and long-words.

7. What is the difference between cycle stealing mode and burst mode Direct Memory Access (DMA)? How does the peripheral controller request each kind of mode when it wishes to transfer data over the system bus?