CMPE 401 - Computer Interfacing

Assignment #4

1. One high-speed scanner and two laser printers are to be connected to a single networked computer. The scanner has a peak data rate of 350 KB/s, while each laser printer has a peak data rate of 210 KB/s. (Recall that 1 KB = 1024 bytes.) Assume that the scanner produces data blocks containing 2048 bytes each. There is an overhead of 130 clock cycles to handle each data block using direct memory access (DMA). Once a DMA transfer begins, the cost of each two-byte word transfer is two clock cycles. Each printer receives data from the CPU using word-sized MOVE instructions, and each MOVE instruction requires eight CPU clock cycles to transfer two bytes of data. At the start of each print job there is an overhead of 300 CPU clock cycles, plus a pause time of 10 milliseconds. Print jobs typically take multiple seconds to complete. What would be the slowest allowable CPU operating frequency (rounded up to the nearest one third of a megahertz) to ensure that the peak work load caused by the scanner and the two printers is less than 10%?

2. The M68000-series microprocessors from Motorola Semiconductor (now called Freescale Semiconductor) provide both user interrupts and autovectored interrupts. How could a "intelligent" peripheral interface chip, one with many different possible sources of interrupts, exploit the user interrupt mechanism to ensure faster interrupt handling?

3. Briefly explain why direct memory access (DMA) is a fast method for transferring large blocks of data? What are the alternatives to using DMA? Why does DMA become less attractive as the number of transferred bytes gets smaller?

4. Double buffers and first-in first-out (FIFO) queues are two different ways of decoupling a producer of data from a consumer of data. What are the principal differences between the two methods? In which situations should one choose one method over the other? (Be sure to consider scenarios that are favourable to double buffers and to FIFO queues.)

5. Consult the on-line documentation for the TPU (available by following the link from the course homepage) to determine how the "Period Measurement with Additional/Missing Transition Detect" built-in function works (function code $B). Briefly explain the capabilities of this function in your own words.

6. In the lectures we saw that the registers of the DUART can, depending on the implemented memory map, be located eitherr on (a) subsequent even addresses, (b) subsequent odd addresses, or (c) packed adjacent addresses. On the other hand, the registers of the TPU are only located at even addresses. Briefly explain where the three possibilities arise for the DUART registers offsets, and also explain why the TPU register offsets are even.

7. Assume that the TPU is being used with a TCR1 clock frequency of 16.78 MHz, divided down by a factor of 64. Assume further that there are to be 12 different stepping rates. Calculate the corresponding values of the STEP_CNTL0 and STEP_CNTL1 parameters if the slowest stepping rate is to be 16 steps/second and the maximum stepping rate is to be 240 steps/second.