CMPE 401 – Computer Interfacing

Model Solutions to the Midterm Examination

Instructor: B. F. Cockburn

Exam date: November 5, 2004

Exam duration: 50 minutes

Aids permitted: A hardcopy of the course overheads can be freely consulted.

Model solutions to past assignments can be freely consulted.

A 68000 Programming Reference Card

Electronic calculators are permitted.

Instructions: 1. Provide your name printed, signature and I.D. number on this page.

2. Verify that this booklet contains 7 pages (including the cover page)

3. Neatly enter your answers in the spaces provided.

4. Use the reverse sides of the pages for rough work.

Student name: ___________________,_______________

Last name First name

Signature: ___________________________________

Student I.D.: ___________________________________

Question	Time	Worth	Mark	Subject
1.	13	26		Terminology
2.	14	28		MicroC/OS-II
3.	16	32		Hardware Interrupts
4.	7	14		Saving CPU Registers
Total	50 mins	100

Question # 1 (Terminology)

What is meant by each of the following abbreviations. Briefly explain the significance of each concept in Computer Interfacing.

(a) TCP

[8 marks]

Transmission Control Protocol (TCP) is the transport layer protocol that is used in the Internet to ensure reliable end-to-end transmission of streams of application bytes traveling in both directions between two communicating computers. TCP uses the unreliable datagram services provided by the Inter-networking Protocol (IP) at the next lower layer in the standard TCP/IP communications protocol stack. TCP is in turn used by higher layer application protocols, such as “telnet”, “ftp”, and “http”.

Because of the central role played by TCP in making the worldwide Internet possible (by allowing different, not perfectly reliable networks to be linked together), TCP is clearly of importance to computer interfacing. More and more computer interfacing problems require interaction with and hence knowledge of TCP. More and more computer-controlled and computer-monitored actions occur over the Internet.

(b) TCB

[8 marks]

A Task Control Block (TCB) is a data structure that is used in multitasking kernels, like MicroC/OS-II, to store the state of a task in between the times when it is executing on the Central Processing Unit (CPU). The task state includes the contents of all of the CPU registers.

Tasks are an effective way of partitioning the software in a computer system into smaller and simpler pieces. For that reason, tasks may be a convenient way of simplifying a computer interfacing problem. Different activities in the system can be controlled by dedicated tasks. The TCB is an essential part of a multitasking kernel which allows it to correctly stop and then later restart tasks.

Question # 1 (Terminology, cont’d)

[10 marks]

Direct Memory Access (DMA) is a data transfer technique that uses a special control circuit, called a DMA Controller (DMAC), to conduct the transfer over the system bus. The CPU is required to configure the DMAC before the DMA transfer is started. Typically the DMAC interrupts the CPU as soon as the DMA transfer has completed. The DMAC produces the bus signals that are required to move the data bytes from the source (either an input device or a memory buffer area) to the destination (either an output device or a memory buffer area). The DMA mechanism may permit the CPU to share the system bus with the DMAC as the DMA is proceeding. Several DMA transfers may also occur at the same time, sharing the same system bus with each other and the CPU.

The main advantage of DMA transfer or CPU-controlled data transfer using MOVE instructions is that the overhead of executing a large number of MOVE instructions is avoided. The DMA transfer does not require multiple instructions to be fetched and decoded. Thus for large transfers, especially, DMA offers much faster data transfers. For this reason, DMA is a very common technique in computer interfacing problems where large quantities of data need to be transferred very fast.

Question # 2 (MicroC/OS-II)

(a) MicroC/OS-II associates a priority level for each task in the system. No more than one task can have the same priority level. Briefly explain why such priorities are provided in MicroC/OS-II. Why are task priorities useful to have in real time systems?

[14 marks]

Task priorities are provided in MicroC/OS-II to allow the software designer to ensure the orderly and predictable handling of more important and/or more time-critical activities. In MicroC/OS-II the lower the priority number, the higher its priority in gaining use of the CPU. The highest priority ready-to-run CPU is always the task that is given access to the CPU. The currently executing task gives up the CPU only if it wants to (e.g. by terminating or suspending itself) or if it becomes blocked when waiting on an event (e.g. waiting for a semaphore to be signaled or waiting for a message to be deposited into an empty message queue).

Task priorities are useful to have in a multitasking environment because they ensure deterministic (i.e. predictable) and fast handling of important events. Important events can be handled by higher priority tasks. The behaviour of higher priority tasks need not be affected by the presence and/or the activities of lower priority tasks.

Question # 2 (MicroC/OS-II, cont’d)

(b) In interrupt service routines in MicroC/OS-II, why are we required to include a jump to the routine OSIntExit68K, without including an RTE instruction? Briefly explain what actions must occur as a result of executing this routine.

[14 marks]

OSIntExit68K is a routine that performs several operations. It must undo the actions that occur when an interrupt service routine (ISR) is entered. These actions at the start of an ISR actions include: (1) saving the return address (PC) of the interrupted code and the contents of the status register (SR) onto the supervisor stack; (2) incrementing the global variable OSIntNesting; and (3) saving the contents of CPU registers A0-A6 and D0-D7 onto the supervisor stack. Thus to terminate an ISR, OSIntExit68K must take care of (1) removing the contents of A0-A6 and D0-D7 from the supervisor stack; (2) decrementing OSIntNesting; and (3) removing the saved return address and status register contents from the supervisor stack. This last step performs the actions (restoring SR and PC) that would normally be done by an RTE instruction, so the RTE instruction is not required in the ISR if OSIntExit58K is called.

The PC, SR and registers A0-A6 and D0-D7 must be loaded by OSIntExit68K with the contents corresponding to the task that should be running after the ISR as finished. This task will be the originally interrupted task if this task is still the highest priority task that is ready to run. However, the actions of the ISR may cause a higher priority task to become ready-to-run. OSIntExit68K looks out for this possibility. If it occurs, then the interrupted task is not restored to the CPU but its state is instead loaded into a Task Control Block, which is then added to the ready-to-run queue. The CPU registers are then loaded from the values that were stored previously in the higher priority task’s TCB. Then the higher priority task resumes execution on the CPU.

Question # 3 (Hardware Interrupts)

(a) There can be several different sources of hardware interrupts in a microcomputer. Two or more of these interrupts can be active at the same time. Briefly describe how the 68332 microcontroller handles multiple active interrupts in a predictable and safe way.

[16 marks]

Each possible IRQ is assigned (using hardware connections or initialization software) to one of the seven possible Interrupt Priority Levels (IPLs). IPL = 0b001 is the lowest priority, and 0b111 is the highest priority. IPL = 0b000 means no interrupts are active. Only the active IRQ with the highest IPL is passed on to the CPU by an interrupt priority encoder circuit. The IPL bits in the CPU’s status register are set according to the IPL of the IRQ currently being serviced. The IPL bits are 0b000 if no interrupt is being serviced. Newly arriving IRQs IPLs from 0b000 to 0b110 are blocked if the the IPL bits are at the same or a higher level. An IRQ with IPL = 0b111 is never blocked (it is a nonmaskable IRQ), and always interrupts the currently running routine.

(b) What is an interrupt vector, and what is it used for in a microcomputer? What is the difference between an interrupt autovector and a user interrupt vector?

[16 marks]

An interrupt vector is the address of an interrupt service routine (ISR). All of the interrupt vectors are stored in long-word locations in the CPU’s exception vector table. There are 7 autovectors in this table to hold the starting addresses of the ISRs for the seven possible interrupt priority levels. These autovectors are used to locate the ISR for each priority level when autovectoring is being used (say if the AVEC signal is tied active/low in the 68332). There are also 192 user interrupt vectors in the exception vector table, which are selected using a exception number that is passed from the interrupting device to the CPU during an interrupt acknowledgement cycle (IACK cycle). To start the IACK cycle, the CPU sets the three function control bits to 0b111, and then drives the active IPL number onto address lines A3, A2 and A1. The interrupting device must then respond by dumping the exception vector number onto D7-D0 of the data bus so that the CPU can find the correct user interrupt vector.

Question # 4 (Saving Registers)

In the laboratory exercises there have been three different situations where we have saved some or all of the CPU registers on to the stack: (1) in interrupt service routines, (2) in subroutines, and (3) when calling a compiled C routine from an assembly language routine. Briefly explain why the registers need to be saved and then later restored in each of these three situations. In each situation, how would one determine which registers need to be saved.

[14 marks]

(a) When the CPU decides to service an interrupt request, the IRQ can occur at any arbitrary time. To be able to safely restore the interrupted program, both the SR and PC are automatically saved on the stack. It is the responsibility of the ISR to also save onto the supervisor stack all registers that may get changed by the ISR (e.g. some or all of D0-D7 and A0-A6). Otherwise, the interrupt service routine may inadvertently corrupt the contents of registers that are being used by the interrupted program.

(b) When a subroutine is called, only the PC is auto-matically saved on the stack (user stack if S=0, or supervisor stack if S=1). The SR cannot be saved since that might allow a user mode program to restore the CPU state with S=1; only the Condition Code Register (CCR) can be optionally saved on the stack. Also, it is the responsibility of the subroutine to also save all registers that may get changed by the subroutine (e.g. some or all of D0-D7 and A0-A6) must be saved on the supervisor stack. Otherwise, the subroutine may inadvertently corrupt the contents of registers that are being used by the interrupted program.

(c) When a C program is called from an assembly language program, unless it has detailed knowledge of the compiler conventions with respect to register usage, it cannot assume that any of the registers will be left untouched by the execution of the compiled routine. To protect itself from unexpected corruption of register contents, the assembly language routine should save all of the CPU registers onto the stack before called the compiled code. After returning from the compiled code, the original register contents can then be restored from the copies on the stack.