CMPE 401 - Computer Interfacing

Assignment #5 Solutions

1. Consider a computer-controlled security system that has 1000 sensors scattered throughout a university campus. Each sensor input records the status (0 => secured, 1 => unsecured) of windows and doors. The sensor inputs are bundled into groups containing 16 signals each. The signals in each group are wired to the 16 inputs of a different memory-mapped register. The sensor inputs need to be scanned at least 12 times per second. Assume that reading one register and determining whether or not it contains all-0s takes 8 CPU clock cycles, and assume further that the CPU clock runs at 16.67 MHz. Determine the polling overhead for the security system. How much slower could the CPU clock be operated without exceeding 10% polling overhead?

   [10 marks]
   (a) Number of 16-bit registers = 1000 / 16 = 62.5
                                          = 63 (rounded up)
   
       Clock cycles to scan all sensors once = 63 x 8 = 504 cycles
   
       Polling overhead = (12 x 504) / 16670000 = 0.03628%
   
   (b) (12 x 504) / 0.10 = 60.48 KHz
   

2. You are to compare the efficiency of two alternative methods for transferring blocks of data from a DVD interface to the frame buffer of a graphics subsystem. Each block of data encodes an image that contains three bytes per pixel in a 1024 x 768 pixel array. Thirty blocks of data must be transferred per second. For the purposes of this problem, efficiency is defined as the fraction of clock cycles that are required to do the transfer. Assume that the system clock runs at 133 MHz and that the data bus width is 32 bits. The two methods that are to be compared are as follows:
   • The first method uses a sequence of MOVE instructions in a loop executing on the CPU. Each MOVE instruction takes 6 clock cycles to execute. To increase the efficiency, 48 MOVE instructions are contained inside an execution loop. The loop is controlled by a conditional branch instruction that takes 8 clock cycles to execute. This loop forms the body of an interrupt service routine (ISR). You are to assume that block transfers are to be started by an interrupt signal produced by the DVD interface. The overhead of responding to the interrupt and going to the start of the ISR, and returning from the end of the ISR, is a total of 80 clock cycles.
   • The second method uses the direct memory access (DMA) method. A block transfer begins when the DVD interface asserts a REQUEST signal that goes to a DMA controller (DMAC). The DMAC responds by interrupting the CPU (80 clock cycles overhead). The CPU then initializes the DMAC for the transfer (100 clock cycles). From that point, the DMAC starts to transfer the block of data from the DVD interface to the graphics buffer using the cycle stealing method. The DMAC asserts a DRIVE signal to tell the DVD interface to drive the next 32-bit word of data onto the data bus. When DRIVE is de-asserted by the DMAC, the DVD interface stops driving the data bus lines. If DRIVE is held asserted high, then the peripheral chip will automatically drive a sequence of new 32-bit data words, with one new word appearing every clock cycle.

   [20 marks]
   Number of bytes per block = 3 x 1024 x 768 = 2359296
   

   • Using MOVE instructions executing on the CPU:
     Bytes moved per 48 MOVE instructions = 48 x 4 = 192
     Number of loop iterations per block = 2359296 / 192 = 12288
     Clock cycles per block = 12288 x ((6 x 48) + 8) = 3637248
     Overhead = (30 x 3637248) / 133000000 = 82.0432%
   • Using direct memory access (DMA):
     Clock cycles per block = 80 + 100 + (2359296 / 4) = 590004
     Overhead = (30 x 590004) / 133000000 = 13.3084%

3. The MC68332 system expansion bus has four signals (SIZ0, SIZ1, DSACK0 and DSACK1) that are used to resize the data bus transfers to suit the data port size of the addressed device. Briefly explain the sequence of operations that occur during one bus operation that allow the bus to be resized to accommodate byte-sized, word-sized and longword-sized write operations to both 8-bit and 16-bit wide peripheral data ports.

   [25 marks]
   SIZ1 and SIZ0 are signals that are used by the present bus master, usually the CPU, to indicate the size (measured in bytes) of the ongoing data transfer. The two size signals are valid at the same time as the address signals, that is, when the address strobe (AS) is asserted low. The coding used by SIZ1 and SIZ0 is as follows:

   SIZ1	SIZ0	Transfer Size
   L	H	1 byte
   H	L	2 bytes
   H	H	3 bytes
   L	L	4 bytes

   DSACK1 and DSACK0 (data and size acknowledge) are two active low signals that are used by a memory-mapped device to both (1) indicate to the bus master how big its data port is (either 8-bit or 16-bit), and (2) indicate to the bus master that it has had enough time to complete the bus operation (either a read or a write operation). Eight-bit ports are assumed to be connected to data bus lines D15-D8 (these 8 data bus lines correspond to bits 7-0 in the CPU data registers, for transfers to/from the 8-bit port). As long as DSACK1 and DSACK0 are held high (inactive), then wait states are automatically inserted (up to some maximum limit). If the port is 8-bit and the port has finished the transfer, then DSACK0 is asserted low while DSACK1 is left de-asserted high. If the port is 16-bit and the port has finished the transfer, then DSACK1 is asserted low while DSACK0 is left de-asserted high. The case when both DSACK1 and DSACK0 are both asserted low is not defined and should not occur in normal operation.

   When a bus transaction starts, the CPU does not know the port size of the addressed device. The CPU asserts the SIZx signals and external logic is responsible for correctly manipulating the DSACKx return signals to let the CPU know how big the port size is. If a long word is being transfered and the port size is 16 bits, then the CPU transfers the high-order word (bytes 0 and 1) in a first bus operation, and the low-order word (bytes 2 and 3) in a second bus operation. If a long word is being transfered and the port size is 8 bits, then bytes 0, 1, 2 and 3 are transfered, in that order, in four separate bus operations. If a word is being transfered to an 8-bit port, then bytes 0 and 1 are transfered, in that order, in two separate bus operations. Word transfers to a 16-bit port, and byte transfers to an 8-bit port, occur in a single bus operation.

4. Consult either the on-line documentation or the textbook, and then briefly explain how the test-and-set (i.e. TAS) instruction works. Why does this instruction require a special indivisable read-modify-write bus operation instead of read bus operation followed by a write bus operation?

   [15 marks]
   The TAS is used in multiprocessor systems to provide a hardware binary semaphore. The TAS goes and fetches the specified byte-sized destination operands, clears CCR bits V and C, and updates CCR bits N and Z according to the byte value. Finally, the byte is written back to memory with bit #7 forced to value 1. If two or more CPUs share the same system bus and they all attempt to execute a TAS at the same time, then only one of them can be allowed to read the byte and update it first. If the byte starts off cleared, then the first CPU will have its CCR updated with Z=1 and N=0; all of the other CPUs will have Z=0 and N=1. Thus the first CPU can determine that it was first, and the other CPUs can determine that they were not first. The first CPU can then proceed, say to access a shared resource, while the other CPUs wait their turn. For TAS to work properly, the system bus cannot be relinquished by the CPU in between the time when the data byte is read (to update the CCR) and written (with bit #7 set to 1). The TAS is the only 68000 instruction to use a special read-modify-write instruction that prevents any other bus operations from occurring between the TAS read and TAS write.

5. Briefly explain how the three DMA signals in the MC68340 (DREQx, DACKx and DONEx, where x is 1 or 2) are used to implement cycle stealing data transfers. Consider only single-address write operations. Hint: refer to chapter 11 of the course notes and/or the on-line User Manual for the MC68340.

   [15 marks]
   DREQ0 (also, DACK1) is an active low input to the 68340 that is used by a peripheral controller to request a DMA word (or byte) transfer.

   DACK0 (also, DACK1) is an active low output from the 68340 to the peripheral controller that indicates that a DMA word (or byte) transfer will occur in the present bus operation. In two address DMA (e.g. transfers from one memory region to a second memory region), DACKx is asserted in the read bus cycle, immediately before the corresponding write bus cycle.

   DONE0 (also, DONE1) is at different times an active low input to the 68340 and an active low output from the 68340. As an input to the 68332, DONEx indicates to the DMAC in the 68340 that then next DMA word (or byte) to be transferred will be the last one in the present block. As an output from the 68332, DONEx is asserted to confirm that the present DMA word (of byte) being transferred is the last one in the block.

6. Explain how open collectors are used in the GPIB data transfer operation to implement a multilateral asynchronous bus protocol.

   [15 marks]
   Open collector drivers are used to drive two handshake signals, "Not ready for data (NRFD)" and "Not data accepted (NDAC)", that are essential for implementing the GPIB protocol. The currently active GPIB talker must wait until the NRFD line is pulled high passively by a pull-up resistance before it can assert the "Data valid (DAV)" line. A high NRFD signal will only happen once *all* of the listeners on the GPIB have stopped driving NRFD low with their open collector drivers. Thus the active talker, by monitoring NRFD, can determine when the *slowest* listener among possibly many listeners is ready to receive the next byte of data over the data I/O lines.

   Once NRFD goes high, the active talker asserts the DAV signal low. The one or more active listeners will then start to assert NRFD low. However, the open collector driver of the fastest-reacting listener will, on its own, drive NRFD low.

   In the same way, the active talker must wait for the slowest active listener to stop driving NDAC low using its open collector driver before the talker can drive DAV back high again at the end of a data transfer. Once the slowest listener has stopped activating its open collector driver, the NDAC signal is pulled high passively by an external resistance. After the active talker sees NDAC go high, it deasserts DAV high and thus terminates the data transfer.

   Thus the use of open collectors to drive NRFD and NDAC allows the one active talker to send data safely to a multitude of possible listeners even if the listeners have very different response times.