CMPE 401 - Computer Interfacing

Assignment #5

1. Consider a computer-controlled security system that has 1000 sensors scattered throughout a university campus. Each sensor input records the status (0 => secured, 1 => unsecured) of windows and doors. The sensor inputs are bundled into groups containing 16 signals each. The signals in each group are wired to the 16 inputs of a different memory-mapped register. The sensor inputs need to be scanned at least 12 times per second. Assume that reading one register and determining whether or not it contains all-0s takes 8 CPU clock cycles, and assume further that the CPU clock runs at 16.67 MHz. Determine the polling overhead for the security system. How much slower could the CPU clock be operated without exceeding 10% polling overhead?

2. You are to compare the efficiency of two alternative methods for transferring blocks of data from a DVD interface to the frame buffer of a graphics subsystem. Each block of data encodes an image that contains three bytes per pixel in a 1024 x 768 pixel array. Thirty blocks of data must be transferred per second. For the purposes of this problem, efficiency is defined as the fraction of clock cycles that are required to do the transfer. Assume that the system clock runs at 133 MHz and that the data bus width is 32 bits. The two methods that are to be compared are as follows:
   • The first method uses a sequence of MOVE instructions in a loop executing on the CPU. Each MOVE instruction takes 6 clock cycles to execute. To increase the efficiency, 48 MOVE instructions are contained inside an execution loop. The loop is controlled by a conditional branch instruction that takes 8 clock cycles to execute. This loop forms the body of an interrupt service routine (ISR). You are to assume that block transfers are to be started by an interrupt signal produced by the DVD interface. The overhead of responding to the interrupt and going to the start of the ISR, and returning from the end of the ISR, is a total of 80 clock cycles.
   • The second method uses the direct memory access (DMA) method. A block transfer begins when the DVD interface asserts a REQUEST signal that goes to a DMA controller (DMAC). The DMAC responds by interrupting the CPU (80 clock cycles overhead). The CPU then initializes the DMAC for the transfer (100 clock cycles). From that point, the DMAC starts to transfer the block of data from the DVD interface to the graphics buffer using the cycle stealing method. The DMAC asserts a DRIVE signal to tell the DVD interface to drive the next 32-bit word of data onto the data bus. When DRIVE is de-asserted by the DMAC, the DVD interface stops driving the data bus lines. If DRIVE is held asserted high, then the peripheral chip will automatically drive a sequence of new 32-bit data words, with one new word appearing every clock cycle.

3. The MC68332 system expansion bus has four signals (SIZ0, SIZ1, DSACK0 and DSACK1) that are used to resize the data bus transfers to suit the data port size of the addressed device. Briefly explain the sequence of operations that occur during one bus operation that allow the bus to be resized to accommodate byte-sized, word-sized and longword-sized write operations to both 8-bit and 16-bit wide peripheral data ports.

4. Consult either the on-line documentation or the textbook, and then briefly explain how the test-and-set (i.e. TAS) instruction works. Why does this instruction require a special indivisable read-modify-write bus operation instead of read bus operation followed by a write bus operation?

5. Briefly explain how the three DMA signals in the MC68340 (DREQx, DACKx and DONEx, where x is 1 or 2) are used to implement cycle stealing data transfers. Consider only single-address write operations. Hint: refer to chapter 11 of the course notes and/or the on-line User Manual for the MC68340.

6. Explain how open collectors are used in the GPIB data transfer operation to implement a multilateral asynchronous bus protocol.