CMPE 401 - Computer Interfacing

Assignment #5 Solutions

1. Using the timing specifications provided in chapter 11 of the course notes, determine the following time intervals:
   • The maximum time from the rising edge of the first CLKOUT period in a write bus operation, to the time when address lines A20 to A23 are valid.
   • The minimum time from the time that the read/write signal goes low in a write bus operation, until the time when the address strobe goes active low.
   • The minimum time from the time that the read/write signal goes low in a write bus operation, until the time when the databus drivers start to drive the new data values.
   • The maximum time from the rising edge of the first CLKOUT period in a read bus operation to the time that the databus drivers are turned off (tri-stated) from a preceding write bus operation.
   • The minimum time that the databus signals must be driven in a bus read operation after the time that the data strobe signal goes high (inactive).

   The five time intervals are as follows (assuming a 16.78 MHz clock)
   from Table A-6 in the User Manual of the 68332:
   (a) Clock high to address (interval #6): 29 ns max
   (b) Clock high to AS asserted (interval 21): 15 ns min
   (c) R/W asserted low to data bus driven (interval 55): 40 ns min
   (d) Clock high to data out tri-stated (interval 54): 28 ns max
   (e) DS negated to data out invalid (interval 25): 15 ns min
   

2. Referring to page 11-32 in the course notes, briefly explain how the CPU reads a four-byte long-word from a location in a 16-bit device. Before reading from the 16-bit location, the CPU does not know whether the location is 8, 16 or 32-bits wide. Note that signals SIZ0 and SIZ1 are outputs from the CPU, and DSACK0 and DSACK1 are inputs to the CPU that are generated either by the peripheral devices themselves or, more likely, by address decoding logic.

   When the CPU begins the read bus operation, it sets SIZ0 to L and SIZ1 
   to L to signal its desire to read a four-byte long word that starts at 
   the address given on the address bus lines.  The 16-bit device responds 
   by driving DSACK1 low (active), while leaving DSACK0 high (inactive), 
   to warn the CPU that it will be returning only two bytes (the two most 
   significant bytes of the long word requested by the CPU).
   
   After latching the first two bytes off of the data bus, the CPU must
   then begin a second read bus operation to obtain the second two bytes
   of the long word.  It does this by setting SIZ0 to L and SIZ1 to H 
   (to indicate the CPU's desire for two bytes) and also adjusting the 
   address to point to the first byte of second word (the third byte in 
   the long word that was requested).  The CPU then completes the read 
   bus cycle and latches in the second two bytes.
   
   In this way the CPU adjusts the bus transaction to accommodate different
   sizes in the peripheral devices that it addresses for read operations
   (and also for write operations).
   

3. Determine the input noise margins for the 74LS10 TTL NAND gate. Now determine the noise margins for the TTL 74LS132 NAND gate with Schmitt trigger inputs. You can assume that the output stages of the two gates have the same electrical characteristics.

   For the 74LS10, V_OH = 2.7 V min and V_OL = 0.5 V max.
   For the (regular TTL) inputs, V_IH = 2.0 V min and V_IL = 0.8 V max. 
   Thus, NMH = 2.7 - 2.0 = 0.7 V, and NML = 0.8 - 0.5 = 0.3 V.
   
   For the 74LS132, we will take V_IH to be 0.9 V because once the input
   is recognized as being a 1, the input will still be considered a 1
   even if it falls as low ast 0.9 V.  Similarly, the V_IL will be taken
   as being 1.7 since once the input is taken as being a 0, the input
   will still be considered a 0 even if it rises to 1.7 V.
   Thus, NMH = 2.7 - 0.9 = 1.8 V, and NML = 1.7 - 0.5 = 1.2 V.
   
   Notice how the notice margins have increased for the gate with
   Schmitt trigger inputs compared to a regular TTL gate.
   

4. Use Laplace transform methods to derive the output voltage waveform, Vo(t), given on slide 12-18.

   In the time domain, the output voltage is governed by the current
   flowing into the capacitor as follows:
     Vo(t) = V_L + (1/C_L)*integral(k=0 to t) i(k) dk
               where i(k) = (V_H - Vo(k)) / R_OH
   
   After substituting the expression for i(k) and letting tau = R_OH C_L
   we obtain:
     Vo(t) = V_L + (V_H / tau)*t - (1 / tau)*integral(h = 0 to t) Vo(k) dk
   
   Taking the Laplace transform of both sides:
     Vo(s) = V_L/s + V_H/(tau*(s^2)) - (1/tau*s)*Vo(s)
   
   Solving for Vo(s) gives:
     Vo(s) = (tau*s*V_L + V_H) / (s*(1+tau*s)) 
           = tau*V_L/(1+tau*s) + (1/s)*(V_H/(1+tau*s))
           = V_L/(s+(1/tau)) + (1/s)*(V_H/tau)/(s+(1/tau))
           = V_L/(s+(1/tau)) + V_H*(1/s - 1/(s+(1/tau)))
           = V_H/s * (V_L - V_H)/(s+(1/tau)))
   
   Taking the inverse Laplace transform of both sides gives:
     Vo(t) = V_H + (V_L - V_H)*exp(-t/tau)
           = V_H + (V_L - V_L) - (V_H - V_L)*exp(-t/tau)
           = V_L + (V_H - V_L)*(1 - exp(-t/tau))
   
   This is the required time domain expression for the capacitor voltage.
   

5. Show, analytically, that the 0% to 50%, 0% to 63%, and 10% and 90% rise times for a simple RC output load are equal to 0.69RC, RC, and 2.2RC, respectively.

   The equation given in the notes for an output driver switching
   from low to high at time t=0 is:
     Vo(t) = V_L + (V_H - V_L)*(1 - exp(-t/tau) where tau = R_OH * C_L
   Note that the 0% and 100% voltages are V_L and V_H, respectively.
   The 0% time is t=0, while the 100% time is at positive infinity.
   
   The time to for the voltage to reach 50% is obtained by solving for
   time t in the following equation:
          V_L + 0.50*(V_H-V_L) = V_L + (V_H - V_L)*(1 - exp(-t/tau) 
        =>                 0.5 = 1 - exp(-t/tau) 
        =>                 0.5 = exp(-t/tau) 
        =>             ln(0.5) = -t/tau
        =>                   t = ln(2) * tau
        =>                   t = 0.693147 R_OH C_L
   Therefore the 0% to 50% rise time is 0.69 R_OH C_L very closely.
   
   To find the 63% time, the same approach could be taken as in the
   50% time, as follows:
          V_L + 0.63*(V_H-V_L) = V_L + (V_H - V_L)*(1 - exp(-t/tau) 
        =>                0.63 = 1 - exp(-t/tau) 
        =>                0.37 = exp(-t/tau) 
        =>            ln(0.37) = -t/tau
        =>                   t = ln(1/0.37) * tau
        =>                   t = 0.99425 R_OH C_L
        =>                   t = R_OH C_L   (very closely)
   In fact, working backwords, when t = R_OH C_L exactly, then the
   corresponding time can be shown to be the time when the signal has
   reached 63.21% of its final value.
   
   To find the 10% to 90% rise time, we begin by first finding expressions
   for the 10% and 90% times; then we subtract the two expressions.
        t(10%) = ln(1/(1.00-0.10) * tau = 0.10536052 * tau
        t(90%) = ln(1/(1.00-0.90) * tau = 2.30258509 * tau
   Hence, t(10% to 90%) = 2.19722457 * tau = 2.2 R_OH C_L very closely.
   

6. Using the lumped model of the TTL output circuit given on slide 12-17, determine the 10% to 90% output rise and fall times for a TTL gate driving a 100 pF load over an output wire with a 5 ohm resistance.

   The 2.2RC formula can be used to solve this problem, but the different
   output resistances (for driving up and driving down) of the driver
   need to be used.
   
   The rise time t_LH = 2.2*(70+5)*(100x10^(-12)) = 16.5 nanoseconds
   The fall time t_HL = 2.2*(25+5)*(100x10^(-12)) =  6.6 nanoseconds