CMPE 401 - Computer Interfacing

Assignment #5

1. Using the timing specifications provided in chapter 11 of the course notes, determine the following time intervals:
   • The maximum time from the rising edge of the first CLKOUT period in a write bus operation, to the time when address lines A20 to A23 are valid.
   • The minimum time from the time that the read/write signal goes low in a write bus operation, until the time when the address strobe goes active low.
   • The minimum time from the time that the read/write signal goes low in a write bus operation, until the time when the databus drivers start to drive the new data values.
   • The maximum time from the rising edge of the first CLKOUT period in a read bus operation to the time that the databus drivers are turned off (tri-stated) from a preceding write bus operation.
   • The minimum time that the databus signals must be driven in a bus read operation after the time that the data strobe signal goes high (inactive).

2. Referring to page 11-32 in the course notes, briefly explain how the CPU reads a four-byte long-word from a location in a 16-bit device. Before reading from the 16-bit location, the CPU does not know whether the location is 8, 16 or 32-bits wide. Note that signals SIZ0 and SIZ1 are outputs from the CPU, and DSACK0 and DSACK1 are inputs to the CPU that are generated either by the peripheral devices themselves or, more likely, by address decoding logic.

3. Determine the input noise margins for the 74LS10 TTL NAND gate. Now determine the noise margins for the TTL 74LS132 NAND gate with Schmitt trigger inputs. You can assume that the output stages of the two gates have the same electrical characteristics.

4. Use Laplace transform methods to derive the output voltage waveform, Vo(t), given on slide 12-18.

5. Show, analytically, that the 0% to 50%, 0% to 63%, and 10% and 90% rise times for a simple RC output load are equal to 0.69RC, RC, and 2.2RC, respectively.

6. Using the lumped model of the TTL output circuit given on slide 12-17, determine the 10% to 90% output rise and fall times for a TTL gate driving a 100 pF load over an output wire with a 5 ohm resistance.