CMPE 401 - Computer Interfacing

Assignment #1

1. List ten of the most likely places that you would find a microprocessor or microcontroller in a typical furnished home?

2. The CPU32 microprocessor inside the MC68332 microcontroller requires 2 clock cycles to excute the NOP instruction. Assume that, as with the lab microcomputer, the CPU clock frequency is 16.78 Mhz. Now consider a CPU32 that begins executing a very long program that contains only NOP instructions. This program could be printed out on sheets of paper, with 13 lines every 5 cm, and hence 66 lines per page. Assume that a stack of 500 pages is about 5 cm thick. What would be the thickness of the portion of the program listing corresponding to the instructions that could be executed by the CPU32 in one second?

3. Briefly explain how the data and instruction cache memories inside a modern microprocessor speed up the execution of typical programs.

4. Design a CPU32 assembly language program that retrieves data items that are stored in a packed array containing NUM_RECORDS records. Each record contains the following fields: (1) two 8-bit unsigned integers, (2) one 16-bit integer, (3) two BCD digits, and (4) three ASCII codes. Your program is to receive the following input parameters: (1) a pointer in A0.L to the first byte in the first record; (2) the position in A1.W of the desired record, from 0 up to NUM_RECORDS-1; (3) the identity in D0.B of the requested field, from 0 to 7. The requested information is to be returned in D7.L, right-justified in a field of zeros.

5. Design a subroutine, called TRANSPOSE, that creates a copy of a given two-dimensional source array of bytes in which the storage order has been changed from column major order to row major order, and the bytes have been sign-extended into words. Recall that in column major order, the elements of the first column are stored first (while incrementing the row position), then the elements of the second column, and so on until the last elements in the last column are stored. In row major order, the elements of the first row are stored first (while increasing the column position), then the elements of the second row, and so on until the last elements of the last row are stored. The base addresses of the source and destination arrays are to be passed as parameters in registers A0.L and A1.L, respectively. The number of rows and columns in the source array are given in registers D5.W and D6.W, respectively. The contents of all CPU registers are to be restored to their original values by the end of the subroutine. Use the LEA instruction to perform any pointer operations.