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Table of Contents

Publications by venues | Publications by topics | FPGA Conferences

2011

  1. Lintao Cui, Jing Chen, Jinjun Xiong and Yu Hu, Acceleration of Multi-Agent Simulation based on FPGA, DATE Workshop W2: Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.
  2. Pengfei Zhu, Ray C.C. Cheung, Hua Li, Lintao Cui and Yu Hu, FPGA Based Acceleration of Graph Similarity, DATE Workshop W2: Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.
  3. Xiaoyu Shi, Dahua Zeng, Yu Hu, Osmar Zaiane and Guohui Lin, Enhancement of Incremental Design for FPGAs Using Circuit Similarity, ISQED, 2011.

2010

  1. Wenyao Xu, Jia Wang, Yu Hu and Lei He, In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults, IEEE Transactions on Circuits and Systems I, 2010.
  2. Xiaoyu Shi, Dahua Zeng, Yu Hu, Osmar Zaiane and Guohui Lin, Accelerating FPGA Design Space Exploration Using Circuit Similarity-Based Placement, FPT, 2010.
  3. Chun Zhang, Yu Hu, Lingli Wang, Lei He and Jiarong Tong, Accelerating Boolean Matching Using Bloom Filter, IEICE Transactions, Vol.E93-A,No.10,Oct. 2010.
  4. Chun Zhang, Yu Hu, Lingli Wang, Lei He and Jiarong Tong, Engineering a Scalable Boolean Matching Based on EDA SaaS 2.0, ICCAD, 2010.
  5. Manu Jose, Yu Hu and Rupak Majumdar, On Power And Fault-Tolerant Optimization In FPGA Physical Synthesis, ICCAD, 2010.
  6. Manu Jose, Yu Hu, Rupak Majumdar and Lei He, Rewiring for Robustness, DAC, 2010. (Best paper award nomination)
  7. Samuel Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, RALF: Reliability Analysis for Logic Faults - An Exact Algorithm and Its Applications, DATE, 2010.
  8. Chun Zhang, Yu Hu, Lei He, Lingli Wang and Jiarong Tong, Building A Faster Boolean Matcher Using Bloom Filter, FPGA, 2010.
  9. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, ASPDAC, 2010.
  10. Yu Hu, Yi-Tao Wang, Adam Stoelting, Yi Zou and Majid Sarrafzadeh, Providing a cushion for wireless healthcare application development, IEEE Potentials Magazine, 2010.

2009

  1. Lei He and Yu Hu, Power-Efficient and Fault-Tolerant Circuits and Systems, ASICON, 2009. (Invited paper)
  2. Zhe Feng, Yu Hu, Lei He and Rupak Majumdar, IPR: In-Place Reconfiguration for FPGA Fault Tolerance, ICCAD, 2009. (Best paper award nomination)
  3. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2009.
  4. Wenyao Xu, Jia Wang, Yu Hu and Lei He, Retiming for Single Event Transient Mitigation in FPGAs, IWLS, 2009.
  5. Zhe Feng, Yu Hu, Rupak Majumdar and Lei He, IPR: InPlace Reconfiguration for FPGA Fault Tolerance, IWLS, 2009.
  6. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, SELSE, 2009.

2008

  1. Yu Hu, Zhe Feng, Rupak Majumdar, and Lei He, Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching, ICCAD, 2008. (Best paper award nomination)
  2. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis, DAC, 2008.
  3. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boo lean Matching for Logic Synthesis of FPGAs, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.
  4. King Ho Tam, Yu Hu, Lei He, Tong Jing and Xinyi Zhang, Dual Vdd Buffer Insertion for Power Reduction, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.
  5. Yu Hu, Yan Lin, Lei He and Tim Tuan, Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2008.
  6. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, and Xianlong Hong, Fashion: A Fast and Accurate Solution to Global Routing Problem, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.
  7. Yu Hu, Zhe Feng, Rupak Majumdar and Lei He, Templates and Algorithms of Boolean Matching for Fault Tolerance in FPGAs, IWLS, 2008.
  8. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching, IWLS, 2008. (Best Contribution Award from Programming Challenge)
  9. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis, IWLS, 2008.

2007

  1. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates. ICCAD, 2007.
  2. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Synthesis Considering Time Variant Temperature Gradient. SRC Techcon Conference, 2007.
  3. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient. ISPD, 2007, pp. 173 - 180.
  4. Yu Hu, King Ho Tam, Tong Jing and Lei He, Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling. SLIP,2007, pp. 95 - 102.
  5. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, and Xianlong Hong. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASPDAC, 2007, pp. 256 - 261.
  6. Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu and Guiying Yan, A full scale solution to the rectilinear obstacle-avoiding Steiner problem, Integration, the VLSI Journal, 2007.
  7. Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu and Guiying Yan, λ-OAT: Lambda-Geometry Obstacle-Avoiding Tree Construction with O(nlogn) Complexity. IEEE Transaction on Computer-Aided Design of Circuits and Systems (TCAD), 26(11), 2007, pp 2073-2079.
  8. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping. IWLS, 2007.
  9. Yu Hu, Satyaki Das and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates. IWLS, 2007.

2006

  1. Yan Lin, Yu Hu, Lei He, and Vijay Raghunat. An Efficient Chiplevel Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction. ISLPED, 2006, pp. 168-173.
  2. Yu Hu, Yan Lin, Lei He and Tim Tuan. Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction. DAC, 2006, pp. 478-483.
  3. Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu and Guiying Yan. An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction in the λ-Geometry Plane. ISPD, 2006, pp. 48-55.
  4. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, and Guiying Yan. DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment. ASPDAC 2006, pp. 618-623.
  5. Yu Hu, Tong Jing, Xian-Long Hong, Zhe Feng, Xiao-Dong Hu, and Gui-Ying Yan, ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm, Journal of Computer Science & Technology, 2006, 21(1), pp. 147-152.

2005

  1. Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, and Guiying Yan. A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS V 2005, LNCS 3553, pp. 344-353.
  2. YangYang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu and Guiying Yan. Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005, pp 198-203.
  3. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An-OARSMan: Obstacle-Avoiding Routing Tree Construction with Good Length Performance. ASPDAC, 2005, pp. 7-12.

2004

  1. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization. ICCCAS 2004, pp. 1276-1280.
  2. Yu Hu, Tong Jing, Xianlong Hong, Qiang Zhou, Ming Shen. A Practical and Efficient Integrated System for VLSI/ULSI Physical Design. ICCCAS 2004, pp. 1233-1237.
 
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