Personal Site

Publications

| journal | Magzine | Conference | Workshop | Technical Reports | Poster | Patent | Dissertation |

Disclaimer: Papers are made available on this webpage to ensure timely dissemination of research results. Copyright and all rights therein are retained by authors or other copyright holders.

Peer Reviewed Journal Articles (selected)
  1. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2009.

  2. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boo lean Matching for Logic Synthesis of FPGAs, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.

  3. King Ho Tam, Yu Hu, Lei He, Tong Jing and Xinyi Zhang, Dual Vd Buffer Insertion for Power Reduction, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.

  4. Yu Hu, Yan Lin, Lei He and Tim Tuan, Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2008.

  5. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, and Xianlong Hong, Fashion: A Fast and Accurate Solution to Global Routing Problem, IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) 2008.

  6. Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu and Guiying Yan, A full scale solution to the rectilinear obstacle-avoiding Steiner problem, Integration, the VLSI Journal, 2007.

  7. Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu and Guiying Yan, Lambda-OAT: Lambda-Geometry Obstacle-Avoiding Tree Construction with O(nlogn) Complexity. IEEE Transaction on Computer-Aided Design of Circuits and Systems (TCAD), 26(11), 2007, pp 2073-2079.

  8. Yu Hu, Tong Jing, Xian-Long Hong, Zhe Feng, Xiao-Dong Hu, and Gui-Ying Yan, ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm, Journal of Computer Science & Technology, 2006, 21(1), pp. 147-152.

Peer Reviewed Magzine Articles

  1. Yu Hu, Yi-Tao Wang, Adam Stoelting, Yi Zou and Majid Sarrafzadeh, Providing a cushion for wireless healthcare application development, IEEE Potentials Magazine, 2010.

Peer Reviewed Conference Papers (selected)
  1. Manu Jose, Yu Hu, Rupak Majumdar and Lei He, Rewiring for Robustness, DAC, 2010. (Best paper award nomination)
  2. Samuel Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, RALF: Reliability Analysis for Logic Faults - An Exact Algorithm and Its Applications, DATE, 2010.

  3. Chun Zhang, Yu Hu, Lei He, Lingli Wang and Jiarong Tong, Building A Faster Boolean Matcher Using Bloom Filter, FPGA, 2010.

  4. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, ASP-DAC, 2010.

  5. Lei He and Yu Hu, Power-Efficient and Fault-Tolerant Circuits and Systems, ASICON, 2009. (Invited paper)

  6. Zhe Feng, Yu Hu, Lei He and Rupak Majumdar, IPR: In-Place Reconfiguration for FPGA Fault Tolerance, ICCAD, 2009. (Best paper award nomination)

  7. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction, ISQED, 2009.

  8. Yu Hu, Zhe Feng, Rupak Majumdar, and Lei He, Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching, ICCAD, 2008. (Best paper award nomination)

  9. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis, DAC, 2008.

  10. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping. ICCAD, 2007.

  11. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates. ICCAD, 2007.

  12. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Synthesis Considering Time Variant Temperature Gradient. SRC Techcon Conference, 2007.

  13. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient. ISPD, 2007, pp. 173 - 180.

  14. Yu Hu, King Ho Tam, Tong Jing and Lei He, Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling. SLIP,2007, pp. 95 - 102.

  15. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, and Xianlong Hong. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC, 2007, pp. 256 - 261.

  16. Yan Lin, Yu Hu, Lei He, and Vijay Raghunat. An Efficient Chiplevel Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction. ISLPED, 2006, pp. 168-173.

  17. Yu Hu, Yan Lin, Lei He and Tim Tuan. Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction. DAC, 2006, pp. 478-483.

  18. Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu and Guiying Yan. An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction in the λ-Geometry Plane. ISPD, 2006, pp. 48-55. 

  19. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, and Guiying Yan. DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment. ASP-DAC 2006, pp. 618-623.

  20. Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, and Guiying Yan. A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS V 2005, LNCS 3553, pp. 344-353.

  21. YangYang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu and Guiying Yan. Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005, pp 198-203.

  22. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An-OARSMan: Obstacle-Avoiding Routing Tree Construction with Good Length Performance. ASP-DAC, 2005, pp. 7-12.

  23. Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization. ICCCAS 2004, pp. 1276-1280.

  24. Yu Hu, Tong Jing, Xianlong Hong, Qiang Zhou, Ming Shen. A Practical and Efficient Integrated System for VLSI/ULSI Physical Design. ICCCAS 2004, pp. 1233-1237.

Peer Reviewed Workshop Papers (w/o proceedings)
  1. Wenyao Xu, Jia Wang, Yu Hu and Lei He, Retiming for Single Event Transient Mitigation in FPGAs, IWLS, 2009.

  2. Zhe Feng, Yu Hu, Rupak Majumdar and Lei He, IPR: InPlace Reconfiguration for FPGA Fault Tolerance, IWLS, 2009.

  3. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, SELSE, 2009.

  4. Yu Hu, Zhe Feng, Rupak Majumdar and Lei He, Templates and Algorithms of Boolean Matching for Fault Tolerance in FPGAs, IWLS, 2008.

  5. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, Mapping and Resynthesis for LUTbased FPGAs with an Efficient SATBased Boolean Matching, IWLS, 2008. (Best Contribution Award from IWLS Programming Challenge)

  6. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis, IWLS, 2008.

  7. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping. IWLS, 2007.

  8. Yu Hu, Satyaki Das and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates. IWLS, 2007.

Technical Reports

  1. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and MacroGates. Technical Report, UCLA Engr 07-264, 2007.

  2. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. Technical Report, UCLA Engr 07-265, 2007.

  3. Yu Hu and Lei He, Retiming for High Performance FPGAs Considering Flipflop Constraints and Process Variations. Technical Report, UCLA Engr 07-266, 2007.

Posters and Presentations
  1. Yu Hu, Robust Logic Synthesis and Its Application on Cyber Physical Systems, IWECS, 2009. (Invited talk)

  2. Yu Hu, Logic Resynthesis for FPGAs by SAT-based Boolean Matching, DAC Ph.D. Forum, 2009. [slides]

  3. Yu Hu, Yan Lin and Lei He, Retiming for High Performance FPGAs Considering Flipflop Constraints and Process Variations. Poster in ISFPGA, 2007.

  4. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient. Student presentation in Electrical Engineering Department Annual Research Review 2007.

  5. Yan Lin, Yu Hu and Lei He, Stochastic Physical Synthesis for FPGA Performance and Yield Optimization, in SRC CADTS Logic and Physical Design Contract Review 2007.

  6. Yan Lin, Yu Hu and Lei He, Stochastic Physical Synthesis Considering Pre-Routing Interconnect Uncertainty and Process Variation, Poster in UCLA Engineering Research Review 2006.

Patents
  1. A method for obstacle-avoiding routing tree construction with good wire-length performance. (Chinese patent pending 200410090885.5. published on 2005/04/06), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

  2. A method for obstacle-avoiding rectilinear Steiner minimum tree construction. (Chinese patent 200410069118.6, granted), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

  3. A method for timing-driven global routing considering coupling effects. (Chinese patent 03124095.X, granted) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

  4. A method for standard cell global routing considering crosstalk reduction. (Chinese patent 02156622.4, granted) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

Dissertation

  1. Yu Hu, Resynthesis Techniques for FPGA Optimization, Ph.D. Dissertation, University of California Los Angeles, 2009.