Error Control Coding

	ERROR CONTROL CODING In our traditional area of error control coding, the laboratory continues to make significant contributions to the implementation of low-power decoding of advanced error control codes, notably of low-density parity check (LDPC) codes. Code design and decoder architecture research have been reported in number of publications. We have designed algorithmic enhancements to deal with the low error floor problem of these codes, as well as with various implementation innovations. Our power sensitive message design methodology was presented as an invited paper at the IEEE International Workshop on Information Theory, held in Lake Tahoe this fall.

ERROR CONTROL CODING

In our traditional area of error control coding, the laboratory continues to make significant contributions to the implementation of low-power decoding of advanced error control codes, notably of low-density parity check (LDPC) codes. Code design and decoder architecture research have been reported in number of publications. We have designed algorithmic enhancements to deal with the low error floor problem of these codes, as well as with various implementation innovations. Our power sensitive message design methodology was presented as an invited paper at the IEEE International Workshop on Information Theory, held in Lake Tahoe this fall.

Multiple Access Interference Control

	Multiple Access Interference Control In our other core area of strength, that of multiple access interference control, we have made several fundamental contributions to joint detection and iterative interference cancellation systems, showing that simple cancellation methods, combined with appropriate error control coding and sophisticated randomized rate and power allocation schemes can approach the physical capacity limit of a multiple access channel. This is achieved by a "modulation" method called partitioned signaling, first studied for code-division multiple-access (CDMA) systems. Partitioned signaling with iterative interference cancellation can rightfully be regarded as a very competitive possible future extension of current simpler detection methods. Future activities will move into the direction of verifying implementability of such systems including prototype transmitter and receiver systems which will benefit from the laboratories expertise in FPGA test implementation techniques. The application of partitioned signaling to multiple antenna systems is being explored in collaboration with industry.

Multiple Access Interference Control

In our other core area of strength, that of multiple access interference control, we have made several fundamental contributions to joint detection and iterative interference cancellation systems, showing that simple cancellation methods, combined with appropriate error control coding and sophisticated randomized rate and power allocation schemes can approach the physical capacity limit of a multiple access channel. This is achieved by a "modulation" method called partitioned signaling, first studied for code-division multiple-access (CDMA) systems. Partitioned signaling with iterative interference cancellation can rightfully be regarded as a very competitive possible future extension of current simpler detection methods. Future activities will move into the direction of verifying implementability of such systems including prototype transmitter and receiver systems which will benefit from the laboratories expertise in FPGA test implementation techniques. The application of partitioned signaling to multiple antenna systems is being explored in collaboration with industry.

Low-complexity VLSI Implementation

	Low-complexity VLSI Implementation In the area of low-complexity VLSI implementation, we have advanced the state-of-the-art know-how on the implementation of high-speed large-scale digital error control decoders. A first test LDPC decoder of size 256 in custom ASIC has been measured and found to be fully functional. A journal paper with these results was published. We are planning the design of a follow-up ASIC decoder using our recent power-efficient messaging concepts as well as advanced low-power circuit implementation methods.

Low-complexity VLSI Implementation

In the area of low-complexity VLSI implementation, we have advanced the state-of-the-art know-how on the implementation of high-speed large-scale digital error control decoders. A first test LDPC decoder of size 256 in custom ASIC has been measured and found to be fully functional. A journal paper with these results was published. We are planning the design of a follow-up ASIC decoder using our recent power-efficient messaging concepts as well as advanced low-power circuit implementation methods.

Analog Signal Processing and Computing

	Analog Signal Processing and Computing In the area of analog signal processing and computing, we have completed the design of an analog discrete Fourier transform processor to act as the analog demodulation front-end of a future all-analog receiver for multi-tone transmission systems. Extensive studies have been carried out on the viability of analog processing for digital data in advanced nano-meter technology, and Professor Schlegel reported on the latest findings of analog processors in an invited paper at the Workshop of Advanced CMOS Technology in Whistler.

Analog Signal Processing and Computing

In the area of analog signal processing and computing, we have completed the design of an analog discrete Fourier transform processor to act as the analog demodulation front-end of a future all-analog receiver for multi-tone transmission systems. Extensive studies have been carried out on the viability of analog processing for digital data in advanced nano-meter technology, and Professor Schlegel reported on the latest findings of analog processors in an invited paper at the Workshop of Advanced CMOS Technology in Whistler.

Networking

	Networking In the area of networking we have investigated the maximum information carrying capacity of ad hoc networks which rely on message routing. It is now fairly well established that the per node capacity in such networks decreases with the square root of the number of users, making large ad hoc networks very inefficient. We have worked out information theoretic bounds on these limits under a variety of conditions and local cooperation strategies, and have shown that the use of joint detection receivers can improve the asymptotic capacity behavior of such networks. More importantly, however, on-going research indicates that the use of some form of joint detection is an absolute must unless lest severe capacity degradations do occur. These results were recently featured in an IEEE Signal Processing Magazine paper.

Networking

In the area of networking we have investigated the maximum information carrying capacity of ad hoc networks which rely on message routing. It is now fairly well established that the per node capacity in such networks decreases with the square root of the number of users, making large ad hoc networks very inefficient. We have worked out information theoretic bounds on these limits under a variety of conditions and local cooperation strategies, and have shown that the use of joint detection receivers can improve the asymptotic capacity behavior of such networks. More importantly, however, on-going research indicates that the use of some form of joint detection is an absolute must unless lest severe capacity degradations do occur. These results were recently featured in an IEEE Signal Processing Magazine paper.

FPGA Technology

	FPGA Technology Work on FPGA Technology headed by our postdoctoral associate has also made great progress. We have completed a versatile channel emulator to be used in our NEWAGE project, as well as novel and extremely accurate noise generators, beta-versions of which have been given to several potential industrial collaborators. We also developed an operating system and visual interface for our FPGA environments, which makes it easier to use them for upcoming tests. A series of demonstration examples were also programmed and demonstrated to visitors in a number of laboratory demonstration tours over the second half of 2007.

FPGA Technology

Work on FPGA Technology headed by our postdoctoral associate has also made great progress. We have completed a versatile channel emulator to be used in our NEWAGE project, as well as novel and extremely accurate noise generators, beta-versions of which have been given to several potential industrial collaborators. We also developed an operating system and visual interface for our FPGA environments, which makes it easier to use them for upcoming tests. A series of demonstration examples were also programmed and demonstrated to visitors in a number of laboratory demonstration tours over the second half of 2007.

Packet Synchronization

	Packet Synchronization In the area of packet synchronization we examined the theory of efficient packet detection in a recent paper. The proposed method was analyzed with quadratic forms using the theory of Lagrange polynomials, and extensions to multi-path fading channels have been discussed and are under way. This methodology will be implemented as proof-of-concept cores on NEWAGE to verify robustness and the reliability provided by the theory.

Packet Synchronization

In the area of packet synchronization we examined the theory of efficient packet detection in a recent paper. The proposed method was analyzed with quadratic forms using the theory of Lagrange polynomials, and extensions to multi-path fading channels have been discussed and are under way. This methodology will be implemented as proof-of-concept cores on NEWAGE to verify robustness and the reliability provided by the theory.